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Nicola Da Dalt
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2010 – 2019
- 2015
- [j15]Federico Cernoia, Davide Ponton, Pierpaolo Palestri, Peter Thurner, Nicola Da Dalt, Giulio Cecco, Luca Selmi:
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique. Int. J. Circuit Theory Appl. 43(6): 709-721 (2015) - [c12]Dmytro Cherniak, Michael Aichner, Roberto Nonis, Nicola Da Dalt:
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. ESSCIRC 2015: 392-395 - [c11]Ken Chang, Frank O'Mahony, Elad Alon, Hyeon-Min Bae, Nicola Da Dalt, Eric Fluhr:
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. ISSCC 2015: 1-2 - 2014
- [j14]Nicola Da Dalt:
An Analysis of Phase Noise in Realigned VCOs. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 143-147 (2014) - [c10]Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon:
F6: Energy-efficient I/O design for next-generation systems. ISSCC 2014: 520-521 - 2013
- [j13]Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. IEEE J. Solid State Circuits 48(12): 3134-3145 (2013) - [c9]Nicola Da Dalt, Peter Pridnig, Werner Grollitsch:
An all-digital PLL using random modulation for SSC generation in 65nm CMOS. ISSCC 2013: 252-253 - [c8]Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. ISSCC 2013: 356-357 - [c7]Nicola Da Dalt, Ajith Amerasekera:
ES3: High-speed communications on 4 wheels: What's in your next car? ISSCC 2013: 515 - 2011
- [j12]Martin Clara, Nicola Da Dalt:
Jitter Noise of Sampled Multitone Signals. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 652-656 (2011) - 2010
- [j11]Stefano Dal Toso, Andrea Bevilacqua
, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa
A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. IEEE J. Solid State Circuits 45(7): 1295-1304 (2010) - [c6]Andrea Bevilacqua
A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. ESSCIRC 2010: 150-153 - [c5]Werner Grollitsch, Roberto Nonis, Nicola Da Dalt:
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. ISSCC 2010: 478-479
2000 – 2009
- 2009
- [j10]Stefan Mendel, Christian Vogel
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 860-864 (2009) - [c4]Stefano Dal Toso, Andrea Bevilacqua
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. ESSCIRC 2009: 444-447 - 2008
- [j9]Luca Bizjak, Nicola Da Dalt, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Luca Selmi:
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1628-1638 (2008) - [j8]Nicola Da Dalt:
Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3663-3675 (2008) - 2006
- [j7]Nicola Da Dalt:
Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1195-1199 (2006) - [c3]Nicola Da Dalt, Claus Kropf, Markus Burian, Thomas Hartig, Hermann Eul:
A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS. ISSCC 2006: 669-678 - 2005
- [j6]Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi:
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. IEEE J. Solid State Circuits 40(6): 1303-1309 (2005) - [j5]Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi:
A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. IEEE J. Solid State Circuits 40(7): 1482-1490 (2005) - [j4]Nicola Da Dalt:
A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(1): 21-31 (2005) - 2004
- [j3]Nicola Da Dalt:
Effect of jitter on asynchronous sampling with finite number of samples. IEEE Trans. Circuits Syst. II Express Briefs 51-II(12): 660-664 (2004) - [c2]Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi:
A low jitter triple-band digital LC PLL in 130nm CMOS. ESSCIRC 2004: 371-374 - [c1]Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi:
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture. ISCAS (4) 2004: 553-556 - 2003
- [j2]Nicola Da Dalt, Christoph Sandner:
A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS. IEEE J. Solid State Circuits 38(7): 1275-1278 (2003) - 2002
- [j1]Nicola Da Dalt, Sven Derksen, Patrizia Greco, Christoph Sandner, Harald Schmid, Klaus Strohmayer:
A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology. IEEE J. Solid State Circuits 37(7): 959-962 (2002)
Coauthor Index
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