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Scott Little
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2010 – 2019
- 2014
- [c14]Andrew N. Fisher, Satish Batchu, Kevin R. Jones, Dhanashree Kulkarni, Scott Little, David Walter, Chris J. Myers
:
LEMA: A tool for the formal verification of digitally-intensive analog/mixed-signal circuits. MWSCAS 2014: 1017-1020 - 2012
- [j5]Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay, Scott Little, John Havlicek, Srikanth Chandrasekaran:
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice. ACM Trans. Design Autom. Electr. Syst. 17(4): 38:1-38:25 (2012) - 2011
- [j4]Scott Little, David Walter
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 617-630 (2011) - [c13]John Havlicek, Scott Little:
Realtime regular expressions for analog and mixed-signal assertions. FMCAD 2011: 155-162 - 2010
- [j3]Scott Little, David Walter
Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. Int. J. Found. Comput. Sci. 21(2): 191-210 (2010) - [c12]John Havlicek, Scott Little, Oded Maler, Dejan Nickovic:
Property-Based Monitoring of Analog and Mixed-Signal Systems. FORMATS 2010: 23-24
2000 – 2009
- 2009
- [c11]Robert A. Thacker, Chris J. Myers
A new verification method for embedded systems. ICCD 2009: 193-200 - 2008
- [b1]Scott Little:
Efficient Modeling and Verification of Analog/Mixed Signal Circuits Using Labeled Hybrid Petri nets. University of Utah, USA, 2008 - [j2]David Walter
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2223-2235 (2008) - 2007
- [c10]David Walter
Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323 - [c9]David Walter
Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. ATVA 2007: 66-81 - [c8]Scott Little, David Walter
Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. ATVA 2007: 114-128 - [c7]Scott Little, Alper Sen, Chris J. Myers
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. MTV 2007: 109-115 - 2006
- [j1]Hao Zheng, Chris J. Myers
Verification of timed circuits with failure-directed abstractions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 403-412 (2006) - [c6]Scott Little, Nicholas Seegmiller, David Walter
Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282 - 2005
- [c5]Chris J. Myers
The Case for Analog Circuit Verification. FAC 2005: 53-63 - 2004
- [c4]Scott Little, David Walter
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440 - 2003
- [c3]Hao Zheng, Chris J. Myers, David Walter
Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35 - 2001
- [c2]Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers
Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI 2001: 132-147 - [c1]Martin Van De Bovenkamp, Ruben Jongkind, Gu Van Rhijn, Frans M. van Eijnatten, Gudela Grote, Jouni Lehtelä, Timo Leskinen, Peter Vink
The E/S Tool IT-Support for Ergonomic and Sociotechnical System Design. ER (Workshops) 2001: 67-80
Coauthor Index
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