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Jens Kargaard Madsen
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2010 – 2019
- 2019
- [j8]Mohammad Tohidi, Jens Kargaard Madsen, Farshad Moradi
:
A low-power, low-noise, high-accurate epileptic-seizure detection system for wearable applications. Microelectron. J. 92 (2019) - [j7]Mohammad Tohidi
Low-Power High-Input-Impedance EEG Signal Acquisition SoC With Fully Integrated IA and Signal-Specific ADC for Wearable Applications. IEEE Trans. Biomed. Circuits Syst. 13(6): 1437-1450 (2019) - [j6]Behzad Zeinali
A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs. IEEE Trans. Emerg. Top. Comput. 7(2): 294-300 (2019) - [i1]Farshad Moradi, Hooman Farkhani, Behzad Zeinali, Hamdam Ghanatian, Johan Michel Alain Pelloux-Prayer, Tim Böhnert, Mohammad Zahedinejad, Hadi Heidari, Vahid Nabaei, Ricardo Ferreira, Johan Åkerman, Jens Kargaard Madsen:
Spin-Orbit-Torque-based Devices, Circuits and Architectures. CoRR abs/1912.01347 (2019) - 2018
- [j5]Hooman Farkhani
A Low-Power High-Speed Spintronics-Based Neuromorphic Computing System Using Real-Time Tracking Method. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 627-638 (2018) - 2017
- [j4]Behzad Zeinali
Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology. Int. J. Circuit Theory Appl. 45(11): 1647-1659 (2017) - [j3]Hooman Farkhani
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 476-487 (2017) - [c15]Hooman Farkhani, Mohammad Tohidi, Sadaf Farkhani, Jens Kargaard Madsen, Farshad Moradi
An energy efficient neuromorphic computing system using real time sensing method. BioCAS 2017: 1-4 - [c14]Behzad Zeinali
Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications. ESSDERC 2017: 172-175 - [c13]Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi
Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching. ICCD 2017: 463-468 - 2016
- [c12]Mohammad Tohidi, Jens Kargaard Madsen, Martijn J. R. Heck, Farshad Moradi
Low-power comparator in 65-nm CMOS with reduced delay time. ICECS 2016: 736-739 - [c11]Mohammad Tohidi, Jens Kargaard Madsen, Martijn J. R. Heck, Farshad Moradi
A low-power analog front-end neural acquisition design for seizure detection. VLSI-SoC 2016: 1-6 - 2015
- [c10]Hooman Farkhani, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi
STT-RAM write energy consumption reduction by differential write termination method. ISCAS 2015: 2936-2939 - [c9]Behzad Zeinali
Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power. ISVLSI 2015: 74-79 - [c8]Hooman Farkhani, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi
Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique. SoCC 2015: 215-220 - 2014
- [j2]Farshad Moradi
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. Microelectron. J. 45(1): 23-34 (2014) - [c7]Farshad Moradi
Robust subthreshold 7T-SRAM cell for low-power applications. MWSCAS 2014: 893-896 - [c6]Hooman Farkhani, Ali Peiravi
Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective. SoCC 2014: 449-454 - [c5]Farshad Moradi
Improved read and write margins using a novel 8T-SRAM cell. VLSI-SoC 2014: 1-5 - [c4]Farshad Moradi
8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology. VLSI-SoC (Selected Papers) 2014: 95-109 - 2012
- [c3]Farshad Moradi
Flip-flop design using novel pulse generation technique. ICECS 2012: 685-688 - 2011
- [c2]Farshad Moradi
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. ICCD 2011: 326-331
1990 – 1999
- 1996
- [j1]Jens Kargaard Madsen, Peter Stuhr Lassen:
A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI. IEEE J. Solid State Circuits 31(10): 1400-1405 (1996) - 1995
- [c1]Jens Kargaard Madsen, Stephen I. Long:
A High-Speed Interconnect Network Using Ternary Logic. ISMVL 1995: 2-7
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