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Mari Yasunaga
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2020 – today
- 2024
- [j1]Junnosuke Suzuki
, Jaehoon Yu
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access 12: 2057-2073 (2024) - [c4]Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Progressive Variable Precision DNN With Bitwise Ternary Accumulation. AICAS 2024: 377-381 - [c3]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
High Throughput Datapath Design for Vision Permutator FPGA Accelerator. ICCE 2024: 1-2 - 2023
- [c2]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura:
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC 2023: 478-485 - [c1]Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits 2023: 1-2
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last updated on 2024-08-01 20:13 CEST by the dblp team
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