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Poul Frederick Williams
2000 – 2009
- 2003
- [j3]Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard:
Satisfiability checking using Boolean Expression Diagrams. Int. J. Softw. Tools Technol. Transf. 5(1): 4-14 (2003) - 2001
- [b1]Poul Frederick Williams:
Formal Verification based on Boolean Expression Diagrams. Electronic Notes in Theoretical Computer Science 56, Elsevier 2001, pp. i-xx, 1-190 - [c3]Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard:
Satisfiability Checking Using Boolean Expression Diagrams. TACAS 2001: 39-51 - 2000
- [j2]Poul Frederick Williams, Macha Nikolskaïa, Antoine Rauzy
:
Bypassing BDD construction for reliability analysis. Inf. Process. Lett. 75(1-2): 85-89 (2000) - [c2]Poul Frederick Williams, Armin Biere, Edmund M. Clarke, Anubhav Gupta:
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking. CAV 2000: 124-138
1990 – 1999
- 1999
- [j1]Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen:
Equivalence checking of combinational circuits using Boolean expression diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 903-917 (1999) - [c1]Poul Frederick Williams, Henrik Hulgaard, Henrik Reif Andersen:
Equivalence checking of hierarchical combinational circuits. ICECS 1999: 355-360
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