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Chaeseok Im
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2010 – 2019
- 2015
- [c9]Shin-gyu Kim, Chaeseok Im, Minwook Ahn, Seungwon Lee:
Source level offloading for special-purpose hardware accelerators. ICCE 2015: 532-533 - 2013
- [c8]Chaeseok Im, Minkyu Jeong, Jaedon Lee, Seungwon Lee:
A dynamically reconfigurable operating system for manycore systems. SAC 2013: 1622-1627 - 2012
- [c7]Chaeseok Im, Minkyu Jeong, Jae Don Lee, Seungwon Lee, Shihwa Lee:
A real-time operating system for manycore systems. SAC 2012: 1845-1846
2000 – 2009
- 2006
- [c6]Keun Soo Yim, Jae Don Lee, Jungkeun Park
, Jeong-Joon Yoo, Chaeseok Im, Yeonseung Ryu:
A Software Reproduction of Virtual Memory for Deeply Embedded Systems. ICCSA (1) 2006: 1000-1009 - 2005
- [j3]Sungchan Kim, Chaeseok Im, Soonhoi Ha:
Schedule-aware performance estimation of communication architecture for efficient design space exploration. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 539-552 (2005) - 2004
- [j2]Chaeseok Im, Soonhoi Ha:
Energy Optimization for Latency- and Quality-Constrained Video Applications. IEEE Des. Test Comput. 21(5): 358-366 (2004) - [j1]Chaeseok Im, Soonhoi Ha, Huiseok Kim:
Dynamic voltage scheduling with buffers in low-power multimedia applications. ACM Trans. Embed. Comput. Syst. 3(4): 686-705 (2004) - [c5]Sungchan Kim, Chaeseok Im, Soonhoi Ha:
Efficient exploration of on-chip bus architectures and memory allocation. CODES+ISSS 2004: 248-253 - [c4]Chaeseok Im, Soonhoi Ha:
Dynamic voltage scaling for real-time multi-task scheduling using buffers. LCTES 2004: 88-94 - 2003
- [c3]Sungchan Kim, Chaeseok Im, Soonhoi Ha:
Schedule-aware performance estimation of communication architecture for efficient design space exploration. CODES+ISSS 2003: 195-200 - [c2]Chaeseok Im, Soonhoi Ha:
An Energy Optimization Technique for Latency and Quality Constrained Video Applications. ESTIMedia 2003: 18-23 - 2001
- [c1]Chaeseok Im, Huiseok Kim, Soonhoi Ha:
Dynamic voltage scheduling technique for low-power multimedia applications using buffers. ISLPED 2001: 34-39
Coauthor Index
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