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Masaya Yoshikawa
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2020 – today
- 2023
- [c84]Yusuke Nozaki
, Shu Takemoto
Hamming Weight aware Fault Analysis for Lightweight Cryptography TWINE. CCIOT 2023: 59-63 - [c83]Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa:
Security Evaluation of Glitch Based Authentication Function for Edge AI. GCCE 2023: 790-791 - [c82]Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa:
Machine Learning Based Power Analysis for Simon with Secure Mechanism. ICCAE 2023: 26-29 - [c81]Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa:
Deep Learning Based Side-Channel Analysis for Lightweight Cipher PRESENT. ICCAE 2023: 570-574 - [c80]Masato Sato
Implementation and Evaluation of the Lightweight Cipher SPARKLE. ICECC 2023: 105-108 - [c79]Ryo Kumagai
Explainable AI based Adversarial Examples and its Evaluation. ICECC 2023: 220-225 - [c78]Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa:
Tamper Resistance Evaluation of Midori128 against Differential Power Analysis. ICKII 2023: 157-160 - 2022
- [c77]Daichi Hirose, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa:
Authenticated Encryption based Secure In-vehicle System against DoS Attacks. GCCE 2022: 44-45 - [c76]Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa:
AI Hardware Oriented Trojan Detection Architecture. ICECC 2022: 9-15 - 2021
- [c75]Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa:
Hardware Trojan for Lightweight Cryptoraphy Elephant. GCCE 2021: 944-945 - [c74]Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa:
Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7. ISDCS 2021: 1-4 - [c73]Yusuke Nozaki, Masaya Yoshikawa:
Neural Network Based Glitch Physically Unclonable Function. UEMCON 2021: 160-164 - 2020
- [c72]Yusuke Nozaki, Masaya Yoshikawa:
Unrolled PRINCE Cipher based Glitch Physically Unclonable Function. ICISS 2020: 3-7 - [c71]Yusuke Nozaki, Masaya Yoshikawa:
Tamper Resistance Evaluation of TWINE Implemented on 8-bit Microcontroller. ICSIM 2020: 226-231
2010 – 2019
- 2019
- [c70]Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa:
Statistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller. IWCIA 2019: 73-76 - [c69]Shu Takemoto, Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa, Shinya Honda, Ryo Kurachi:
Performance Evaluation of CAESAR Authenticated Encryption on SROS2. AICCC 2019: 168-172 - [c68]Yusuke Nozaki, Masaya Yoshikawa:
Countermeasure of Lightweight Physical Unclonable Function Against Side-Channel Attack. CCC 2019: 30-34 - [c67]Yusuke Nozaki, Masaya Yoshikawa:
Secret Sharing Schemes Based Secure Authentication for Physical Unclonable Function. ICCCS 2019: 445-449 - [c66]Masaya Yoshikawa, Yusuke Nozaki:
Side-Channel Analysis for Searchable Encryption System and its Security Evaluation. CSE/EUC 2019: 465-469 - [c65]Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa:
Evaluation of the Hiding-Countermeasure PRINCE Using Differential Power Analysis. GCCE 2019: 164-165 - [c64]Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa:
Security Evaluation of Counter Synchronization Method for CAN Against DoS Attack. GCCE 2019: 166-167 - [c63]Yusuke Nozaki, Masaya Yoshikawa:
Quantitative Performance Evaluation of PL PUF and RO PUF with ASIC Implementation. GCCE 2019: 1127-1128 - [c62]Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa:
Scalability and Performance Evaluation of GA Based Modeling Analysis for RO PUF. GCCE 2019: 1133-1134 - [c61]Yusuke Nozaki, Masaya Yoshikawa:
Side-Channel Resistance Evaluation Method using Statistical Tests for Physical Unclonable Function. ICAIIC 2019: 189-194 - [c60]Yusuke Nozaki, Masaya Yoshikawa:
Security Evaluation of Ring Oscillator PUF Against Genetic Algorithm Based Modeling Attack. IMIS 2019: 338-347 - 2018
- [c59]Susumu Matsumi, Yusuke Nozaki, Masaya Yoshikawa:
Feature Extraction Driven Modeling Attack Against Double Arbiter PUF and Its Evaluation. AICCC 2018: 94-99 - [c58]Yusuke Nozaki, Masaya Yoshikawa:
Security Evaluation of a Lightweight Cipher SPECK against Round Addition DFA. AICCC 2018: 100-105 - [c57]Kazuya Shibagaki, Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa:
Feasibility Evaluation of Neural Network Physical Unclonable Function. GCCE 2018: 712-713 - [c56]Yusuke Nozaki, Masaya Yoshikawa:
Shuffling Based Side-Channel Countermeasure for Energy Harvester. GCCE 2018: 714-715 - [c55]Taichi Umeda, Kazuya Shibagaki, Yusuke Nozaki, Masaya Yoshikawa:
Lethal Genes Aware Genetic Programming Analysis for RO PUF. GCCE 2018: 758-759 - [c54]Yusuke Nozaki, Masaya Yoshikawa:
EM based machine learning attack for XOR arbiter PUF. ICMLSC 2018: 19-23 - [c53]Masaya Yoshikawa, Yusuke Nozaki:
Lightweight Cipher Aware Countermeasure Using Random Number Masks and Its Evaluation. ICVISP 2018: 55:1-55:5 - [c52]Masaya Yoshikawa, Yoshiya Ikezaki, Yusuke Nozaki:
Implementation of Searchable Encryption System with Dedicated Hardware and its Evaluation. UEMCON 2018: 218-221 - 2017
- [c51]Masaya Yoshikawa, Yusuke Nozaki:
Hierarchical power analysis attack for falsification detection cipher. CCWC 2017: 1-6 - [c50]Yoshiya Ikezaki, Yusuke Nozaki, Hideki Nagata, Masaya Yoshikawa:
FPGA implementation technique for power consumption aware tamper resistance accelerator of lightweight PUF. GCCE 2017: 1-2 - [c49]Yusuke Nozaki, Yoshiya Ikezaki, Hideki Nagata, Masaya Yoshikawa:
Power analysis for a lightweight authenticated encryption SIMON-JAMBU. GCCE 2017: 1-2 - [c48]Yusuke Nozaki, Masaya Yoshikawa:
Tamper resistance evaluation of PUF implementation against machine learning attack. ICBEA 2017: 1-6 - [c47]Yusuke Nozaki, Masaya Yoshikawa:
Statistical fault analysis for a lightweight cipher midori. ICIA 2017: 236-241 - [c46]Masaya Yoshikawa, Yusuke Nozaki:
Helper Data Aware Cloning Method for Physical Unclonable Function. SmartCloud 2017: 47-51 - [c45]Masaya Yoshikawa, Yusuke Nozaki:
Electromagnetic analysis method for ultra low power cipher Midori. UEMCON 2017: 70-75 - 2016
- [c44]Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi:
Vulnerability Evaluation Accelerator for Lightweight Ciphers. BigDataSecurity/HPSC/IDS 2016: 377-381 - [c43]Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi:
Multiple Rounds Aware Power Analysis Attack for a Lightweight Cipher SIMECK. BigDataService 2016: 252-256 - [c42]Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa:
Deep learning attack for physical unclonable function. GCCE 2016: 1-2 - [c41]Yusuke Nozaki, Yoshiya Ikezaki, Masaya Yoshikawa:
Hardware Trojan for an authenticated encryption Minalpher. GCCE 2016: 1-2 - [c40]Masaya Yoshikawa, Yusuke Nozaki:
Two Stage Fault Analysis against a Falsification Detection Cipher Minalpher. SmartCloud 2016: 79-84 - 2015
- [j11]Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi:
Secure in-vehicle Systems using Authentication. Int. J. Networked Distributed Comput. 3(3): 159-166 (2015) - [c39]Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi:
Secure in-vehicle systems against Trojan attacks. ICIS 2015: 29-33 - [c38]Takato Iwase, Yusuke Nozaki, Masaya Yoshikawa, Takeshi Kumaki:
Detection technique for hardware Trojans using machine learning in frequency domain. GCCE 2015: 185-186 - [c37]Kohei Nohara, Yusuke Nozaki, Masaya Yoshikawa:
Hardware Trojan for ultra lightweight block cipher Piccolo. GCCE 2015: 202-203 - [c36]Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa:
Statistical fault analysis for a lightweight block cipher TWINE. GCCE 2015: 477-478 - [c35]Masaya Yoshikawa, Takuya Tsukadaira, Takeshi Kumaki:
Design and LSI prototyping of security module with hardware trojan. ICCE 2015: 426-427 - [c34]Yusuke Nozaki, Toshiya Asai, Kensaku Asahi, Masaya Yoshikawa:
Power analysis for clock fluctuation LSI. SNPD 2015: 167-170 - [c33]Masaya Yoshikawa, Yusuke Nozaki, Toshiya Asai, Kensaku Asahi:
Frequency Domain Aware Power Analysis Attack against Random Clock LSI for Secure Automotive Embedded Systems. VTC Fall 2015: 1-5 - 2014
- [j10]Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino:
Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 275-283 (2014) - [c32]Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa:
PUF ID generation method for modeling attacks. GCCE 2014: 393-394 - [c31]Kohei Nohara, Kensaku Asahi, Masaya Yoshikawa:
Study of threat for automotive embedded system by Trojan virus. GCCE 2014: 405-406 - [c30]S. Kiryu, Kensaku Asahi, Masaya Yoshikawa:
Vulnerability evaluation of multiplexing PUF for SVM attacks. ICSEng 2014: 205-210 - [c29]Masaya Yoshikawa, Hikaru Goto, Kensaku Asahi:
Error value driven fault analysis attack. SNPD 2014: 1-4 - 2013
- [c28]Masaya Yoshikawa, R. Satoh, Takeshi Kumaki:
Hardware Trojan for security LSI. ICCE 2013: 29-30 - [c27]Masaya Yoshikawa, Toshiya Asai:
Platform for Verification of Electromagnetic Analysis Attacks against Cryptographic Circuits. ITNG 2013: 653-658 - [c26]Takeshi Kumaki, Masaya Yoshikawa, Takeshi Fujino:
Cipher-destroying and secret-key-emitting hardware Trojan against AES core. MWSCAS 2013: 408-411 - [c25]Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino:
The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. VLSI-DAT 2013: 1-4 - 2012
- [j9]Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino:
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. 95-C(4): 468-477 (2012) - [j8]Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka, Masaya Yoshikawa, Takeshi Fujino:
Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(9): 1518-1528 (2012) - [j7]Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino:
Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2182-2190 (2012) - [c24]Masaya Yoshikawa, Akira Naruse:
Multiplexing aware arbiter physical unclonable function. IRI 2012: 639-644 - 2011
- [j6]Masaya Yoshikawa, Takeshi Fujino:
Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. Int. J. Comput. Their Appl. 18(4): 218-226 (2011) - [c23]Masahiro Fukui, Haruo Miki, Masaya Yoshikawa, Shuji Tsukiyama:
A power grid optimization algorithm considering via reliability. ECCTD 2011: 809-812 - [c22]Masaya Yoshikawa, Y. Kojima:
Efficient Random Number for the Masking Method against DPA Attacks. ICSEng 2011: 321-324 - [c21]Masaya Yoshikawa, M. Sugiyama:
Multi-rounds masking method against DPA attacks. IRI 2011: 100-103 - 2010
- [c20]Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino:
Placement Tool Dedicated for a Via-programmable Logic Device VPEX. CAINE 2010: 21-25 - [c19]Masaya Yoshikawa, Shimohigashi Yoshiaki:
Hybrid Ant Colony Optimization for intensification and diversification. IRI 2010: 359-363
2000 – 2009
- 2009
- [c18]Masaya Yoshikawa, Hidekazu Terai:
Car Navigation System Based on Hybrid Genetic Algorithm. CSIE (5) 2009: 62-65 - [c17]Masaya Yoshikawa, Hidekazu Terai:
OX Hardware Engine for High Speed Character Inheritance. GEM 2009: 43-47 - [c16]Masaya Yoshikawa, Akira Naruse, Shinsuke Souboku:
Adaptive Immune Algorithm Considering Intensification and Diversification. IRI 2009: 422-423 - [c15]Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui:
An Efficient Hardware Accelerator for Power Grid Simulation. ISCAS 2009: 2994-2997 - [c14]Masaya Yoshikawa, Hidekazu Terai:
Dedicated Hardware for Ant Colony Optimization Using Distributed Memory. ITNG 2009: 10-15 - 2008
- [j5]Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai:
Hybrid Architecture of Genetic Algorithm and Simulated Annealing. Eng. Lett. 16(3): 339-345 (2008) - [j4]Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino:
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. IEICE Trans. Electron. 91-C(4): 509-516 (2008) - [c13]Masaya Yoshikawa, Hidekazu Terai:
Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization. GEM 2008: 135-139 - [c12]Masaya Yoshikawa, Hidekazu Terai:
Route selection algorithm based on integer operation Ant Colony Optimization. IRI 2008: 17-21 - 2007
- [j3]Masaya Yoshikawa, Hidekazu Terai:
The new DFM approach based on a genetic algorithm. Artif. Life Robotics 11(1): 28-31 (2007) - [j2]Masaya Yoshikawa, Hidekazu Terai:
Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption. J. Adv. Comput. Intell. Intell. Informatics 11(2): 168-175 (2007) - [c11]Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino:
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. CICC 2007: 261-264 - [c10]Masaya Yoshikawa, Hidekazu Terai:
Architecture for high-speed Ant Colony Optimization. IRI 2007: 1-5 - 2006
- [j1]Masaya Yoshikawa, Hidekazu Terai:
Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. J. Adv. Comput. Intell. Intell. Informatics 10(1): 112-120 (2006) - [c9]Masaya Yoshikawa, Hidekazu Terai:
Co-evolutionary robotics using two kinds of neural networks. CAINE 2006: 330-334 - [c8]Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai:
Immune Algorithm Processor. CATA 2006: 13-18 - [c7]Masaya Yoshikawa, Hidekazu Terai:
Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. SERA 2006: 95-100 - 2005
- [c6]Masaya Yoshikawa, Hidekazu Terai:
Performance driven placement technique based on collaboration of software and hardware. Congress on Evolutionary Computation 2005: 1570-1575 - [c5]Masaya Yoshikawa, Hidekazu Terai:
Hybrid genetic algorithm engine for high-speed floorplanning. ECCTD 2005: 189-192 - [c4]Masaya Yoshikawa, Hidekazu Terai:
A Hierarchical Parallel Placement Technique based on Genetic Algorithm. ISDA 2005: 302-307 - [c3]Masaya Yoshikawa, Hidekazu Terai:
Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. SERA 2005: 130-136 - 2004
- [c2]Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi:
VLSI processor architecture for real-time GA processing and PE-VLSI design. ISCAS (3) 2004: 625-628 - 2002
- [c1]Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi:
Scalable GA processor architecture and its implementation of processor-element. ICASSP 2002: 3148-3151
Coauthor Index
[c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [j11] [c39] [c38] [c37] [c36] [c34] [c33] [c32]
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