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Rochit Rajsuman
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2000 – 2009
- 2006
- [j16]Sunil R. Das, Rochit Rajsuman:
Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. 55(2): 378-380 (2006) - [c23]Rochit Rajsuman:
Innovation In Test: Where Are We. DELTA 2006: 289-294 - [c22]Rochit Rajsuman:
Towards The Methodology of On-line Diagnosis. IOLTS 2006: 76 - 2005
- [j15]Sunil R. Das, Rochit Rajsuman:
Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. 54(5): 1659-1661 (2005) - [j14]Rochit Rajsuman, Masuda Noriyuki, Kazuhiro Yamashita:
Architecture and design of an open ATE to incubate the development of third-party instruments. IEEE Trans. Instrum. Meas. 54(5): 1678-1698 (2005) - 2004
- [c21]Kazumi Hatayama, Rochit Rajsuman:
Opportunities with the open architecture test system. ASP-DAC 2004: 334 - [c20]Rochit Rajsuman:
New opportunities with the open architecture test system. ASP-DAC 2004: 335 - [c19]Rochit Rajsuman:
An Overview of the Open Architecture Test System. DELTA 2004: 341-348 - [c18]Rochit Rajsuman, Masuda Noriyuki:
Open Architecture Test System: System Architecture and Design. ITC 2004: 403-412 - 2003
- [j13]Sunil R. Das, Rochit Rajsuman:
Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)]. IEEE Trans. Instrum. Meas. 52(5): 1350-1352 (2003) - [j12]Rochit Rajsuman:
Architecture, design, and application of an event-based test system. IEEE Trans. Instrum. Meas. 52(5): 1408-1427 (2003) - 2002
- [c17]Rochit Rajsuman:
Extending EDA Environment From Design to Test. Asian Test Symposium 2002: 386-391 - [c16]Rochit Rajsuman:
Testing The Tester. ITC 2002: 27 - [c15]Rochit Rajsuman:
Testing The Tester. ITC 2002: 30 - [c14]Rochit Rajsuman:
Can IC Test Learn from How a Tester is Tested. ITC 2002: 1186 - 2001
- [j11]Rochit Rajsuman, Francky Catthoor:
Guest Editors' Intoduction: The New World of Large Embedded Memories. IEEE Des. Test Comput. 18(3): 3-4 (2001) - [j10]Rochit Rajsuman:
Design and Test of Large Embedded Memories: An Overview. IEEE Des. Test Comput. 18(3): 16-27 (2001) - [c13]Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey H. Dreibelbis:
Test and repair of large embedded DRAMs. I. ITC 2001: 163-172 - 2000
- [j9]Rochit Rajsuman:
Iddq testing for CMOS VLSI. Proc. IEEE 88(4): 544-568 (2000) - [c12]Jerry Katz, Rochit Rajsuman:
A new paradigm in test for the next millennium. ITC 2000: 468-476
1990 – 1999
- 1999
- [c11]Rochit Rajsuman:
Testing a system-on-a-chip with embedded microprocessor. ITC 1999: 499-508 - 1997
- [j8]Suntae Hwang, Rochit Rajsuman:
VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing. VLSI Design 5(3): 299-311 (1997) - 1996
- [c10]Rochit Rajsuman:
Challenge of the 90's: Testing CoreWareTM Based ASICs. ITC 1996: 940 - 1995
- [j7]Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Rochit Rajsuman:
Testable design of BiCMOS circuits for stuck-open fault detection using single patterns. IEEE J. Solid State Circuits 30(8): 855-863 (1995) - 1994
- [j6]Rochit Rajsuman:
A new testing method for EEPLA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 935-939 (1994) - [j5]Rochit Rajsuman, Kamal Rajkanan:
STD Architecture: A Practical Approach to Test M-Bits Random Access Memories. VLSI Design 1(4): 327-334 (1994) - [j4]Rochit Rajsuman:
Special Issue on Digital Hardware Testing. VLSI Design 1(4): i (1994) - [c9]Suntae Hwang, Rochit Rajsuman, Scott Davidson:
IDDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests. VLSI Design 1994: 183-186 - 1993
- [c8]Rochit Rajsuman, David A. Penry:
Coverage of Bridging Faults by Random Testing in IDDQ Test Environment. VLSI Design 1993: 136-139 - 1992
- [c7]David A. Vasko, Rochit Rajsuman:
An analysis and simulation of multiple ring token networks. LCN 1992: 649-657 - [c6]Rochit Rajsuman:
An Architecture To Test Random Access Memories. VLSI Design 1992: 144-147 - 1991
- [c5]Rochit Rajsuman:
An analysis of feedback bridging faults in MOS VLSI. VTS 1991: 53-58 - [c4]Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya, Juney Park:
An analysis and testing of operation induced faults in MOS VLSI. VTS 1991: 137-142 - 1990
- [c3]Suntae Hwang, Rochit Rajsuman, Yashwant K. Malaiya:
On the testing of microprogrammed processor. MICRO 1990: 260-266
1980 – 1989
- 1989
- [j3]Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana:
CMOS stuck-open fault testability. IEEE J. Solid State Circuits 24(1): 193-194 (1989) - [j2]Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya:
CMOS open-fault detection in the presence of glitches and timing skews. IEEE J. Solid State Circuits 24(4): 1055-1061 (1989) - [j1]Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana:
Limitations of switch level analysis for bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7): 807-811 (1989) - [c2]Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya:
CMOS Stuck-open Fault Detection Using Single Test Patterns. DAC 1989: 714-717 - 1987
- [c1]Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana:
On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates. DAC 1987: 244-250
Coauthor Index
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