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Tarik Graba
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2020 – today
- 2023
- [c24]Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo:
Jitter Compensation Mechanism for Dynamic Deterministic Networks. OFC 2023: 1-3 - 2021
- [j7]Ville Yli-Mäyry
, Rei Ueno
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16: 1351-1364 (2021) - [c23]Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger:
RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension. DSD 2021: 325-332 - 2020
- [j6]Rei Ueno
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020) - [c22]Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger:
RISC-V Extension for Lightweight Cryptography. DSD 2020: 222-228
2010 – 2019
- 2019
- [c21]Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Sylvain Guilley, Jean-Luc Danger:
Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations. ICECS 2019: 747-750 - 2018
- [c20]Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD 2018: 508-515 - [c19]Etienne Tehrani, Jean-Luc Danger, Tarik Graba:
Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers. WISTP 2018: 28-43 - 2017
- [j5]Laurent Sauvage
Multi-level formal verification - A new approach against fault injection attack. J. Cryptogr. Eng. 7(1): 87-95 (2017) - [j4]Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin:
Cryptographically Secure Shield for Security IPs Protection. IEEE Trans. Computers 66(2): 354-360 (2017) - 2016
- [j3]Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen:
All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition. IEEE Trans. Circuits Syst. II Express Briefs 63-II(1): 99-103 (2016) - [i2]Sumanta Chaudhuri, Tarik Graba, Yves Mathieu:
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR abs/1609.08681 (2016) - 2015
- [j2]Wei He, Shivam Bhasin, Andrés Otero
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. 9(1): 1-13 (2015) - [c18]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. ICICDT 2015: 1-4 - [c17]Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen:
Hardware implementation of all digital calibration for undersampling TIADCs. ISCAS 2015: 2181-2184 - 2014
- [c16]Maël Berthier, Yves Bocktaels, Julien Bringer, Hervé Chabanne, Taoufik Chouta, Jean-Luc Danger, Mélanie Favre, Tarik Graba:
Studying Leakages on an Embedded Biometric System Using Side Channel Analysis. COSADE 2014: 281-298 - [c15]Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata:
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE 2014: 13 - [c14]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez:
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014: 1-4 - [c13]Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, David Naccache, Xuan Thuy Ngo:
Cryptographically secure shields. HOST 2014: 25-31 - [c12]Shivam Bhasin, Tarik Graba, Jean-Luc Danger, Zakaria Najm:
A look into SIMON from a side-channel perspective. HOST 2014: 56-59 - [c11]Taoufik Chouta, Tarik Graba, Jean-Luc Danger, Julien Bringer, Maël Berthier, Yves Bocktaels, Mélanie Favre, Hervé Chabanne
Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures. HASP@ISCA 2014: 6:1-6:6 - [i1]Maël Berthier, Yves Bocktaels, Julien Bringer, Hervé Chabanne, Taoufik Chouta, Jean-Luc Danger, Mélanie Favre, Tarik Graba:
Studying Potential Side Channel Leakages on an Embedded Biometric Comparison System. IACR Cryptol. ePrint Arch. 2014: 26 (2014) - 2013
- [c10]Florent Lozach, Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger:
FPGA Design of an Open-Loop True Random Number Generator. DSD 2013: 615-622 - [c9]Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger, Yves Mathieu:
Design methodology of an ASIC TRNG based on an open-loop delay chain. NEWCAS 2013: 1-4 - [c8]Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger:
Stochastic Model of a Metastability-Based True Random Number Generator. TRUST 2013: 92-105 - 2012
- [c7]Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba:
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. DSD 2012: 915-922 - 2011
- [c6]Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger:
Efficient Dual-Rail Implementations in FPGA Using Block RAMs. ReConFig 2011: 261-267
2000 – 2009
- 2009
- [j1]Anthony Kolar, Olivier Romain
A System for an Accurate 3D Reconstruction in Video Endoscopy Capsule. EURASIP J. Embed. Syst. 2009 (2009) - [c5]Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger:
WDDL is Protected against Setup Time Violation Attacks. FDTC 2009: 73-83 - [c4]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218 - 2008
- [c3]Sylvain Guilley, Sumanta Chaudhuri
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32 - [c2]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu:
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI 2008: 16-23 - 2006
- [c1]Anthony Kolar, Tarik Graba, Andréa Pinna, Olivier Romain
An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor. ICECS 2006: 144-147
Coauthor Index
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