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Ichiro Hatanaka

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Journal Articles

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2006
[j2]
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Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE J. Solid State Circuits 41(1): 152-160 (2006)
2005
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Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Trans. Electron. 88-C(4): 630-638 (2005)

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