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Priyadarsan Patra
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2020 – today
- 2020
- [j9]Deepa Mathew
, Bijoy Antony Jose
Enabling Hardware Performance Counters for Microkernel-Based Virtualization on Embedded Systems. IEEE Access 8: 110550-110564 (2020) - [j8]Monalisa Mandal
In silico ranking of phenolics for therapeutic effectiveness on cancer stem cells. BMC Bioinform. 21-S(21): 499 (2020)
2010 – 2019
- 2019
- [j7]Jimson Mathew, Bijoy Antony Jose, Priyadarsan Patra
Selected Articles from the ISED 2018 Conference. J. Low Power Electron. 15(2): 160-161 (2019) - [j6]Deepa Mathew, Bijoy Antony Jose, Priyadarsan Patra
Performance Analysis of Microkernel Based Virtualization Techniques on Embedded Systems. J. Low Power Electron. 15(2): 273-281 (2019) - [c19]Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra
Techniques for Debug of Low Power SoCs. MTV 2019: 45-49 - 2017
- [j5]Jimson Mathew, Hafizur Rahaman
Selected Articles from the IEEE ISED 2016 Conference. J. Low Power Electron. 13(4): 605-606 (2017) - 2015
- [j4]Jimson Mathew, Hafizur Rahaman
Selected Articles from the IEEE ISED 2014 Conference. J. Low Power Electron. 11(3): 373-374 (2015) - [c18]Priyadarsan Patra
Fabrics on Die: Where Function, Debug and Test Meet. NOCS 2015: 4:1-4:3 - 2014
- [j3]Jimson Mathew, A. Prasad Vinod
Selected Articles from the IEEE ISED 2013 Conference. J. Low Power Electron. 10(3): 399-400 (2014) - 2013
- [j2]Jimson Mathew, Priyadarsan Patra
Selected Articles from the IEEE ISED 2012 Conference. J. Low Power Electron. 9(3): 302 (2013) - [c17]Arindam Sarkar
Double Layer Perceptron Synchronized Computational Intelligence Guided Fractal Triangle Based Cryptographic Technique for Secured Communication (DLPFT). ISED 2013: 191-195 - [c16]Kanad Basu, Prabhat Mishra
Dynamic Selection of Trace Signals for Post-Silicon Debug. MTV 2013: 62-67 - [c15]Kanad Basu, Prabhat Mishra
Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults. VLSI Design 2013: 291-296 - 2012
- [c14]Kanad Basu, Prabhat Mishra
Constrained signal selection for post-silicon validation. HLDVT 2012: 71-75 - 2011
- [c13]Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra
Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL. ISED 2011: 6-11 - [c12]Kanad Basu, Prabhat Mishra
Efficient combination of trace and scan signals for post silicon validation and debug. ITC 2011: 1-8
2000 – 2009
- 2009
- [c11]Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra
A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. ISQED 2009: 47-54 - 2008
- [c10]Kaiyu Chen, Sharad Malik
Runtime validation of memory ordering using constraint graph checking. HPCA 2008: 415-426 - [c9]Kaiyu Chen, Sharad Malik
Runtime Validation of Transactional Memory Systems. ISQED 2008: 750-756 - [c8]Bin Li, Li-Shiuan Peh, Priyadarsan Patra
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration. NOCS 2008: 117-126 - 2007
- [j1]Priyadarsan Patra
On the cusp of a validation wall. IEEE Des. Test Comput. 24(2): 193-196 (2007) - 2003
- [c7]Kavel M. Büyüksahin, Priyadarsan Patra
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. ISLPED 2003: 294-297 - 2002
- [c6]B. Chappell, Xinning Wang, Priyadarsan Patra
A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD 2002: 164-
1990 – 1999
- 1997
- [c5]Priyadarsan Patra
Delay Insensitive Logic for RSFQ Superconductor Technology. ASYNC 1997: 42-53 - 1996
- [c4]Priyadarsan Patra
Efficient Delay-Insensitive RSFQ Circuits. ICCD 1996: 413-418 - 1995
- [c3]Priyadarsan Patra
Power-efficient delay-insensitive codes for data transmission. HICSS (1) 1995: 316-323 - [c2]Priyadarsan Patra
Fully asynchronous, robust, high-throughput arithmetic structures. VLSI Design 1995: 141-145 - 1994
- [c1]Priyadarsan Patra
Efficient building blocks for delay insensitive circuits. ASYNC 1994: 196-205
Coauthor Index
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