default search action

combined dblp search
author search
venue search
publication search

ask others

Sourindra Chaudhuri

Sourindra M. Chaudhuri

> Home > Persons

Person information

Refine list

refinements active!

zoomed in on ?? of ?? records

view refined list in

export refined list as

showing all ?? records

2010 – 2019

see FAQ

What is the meaning of the colors in the publication lists?

2016
[j3]
- view
  authority control:
- export record
  dblp key:
  - journals/jetc/ChaudhuriJ16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jetc/ChaudhuriJ16
Sourindra M. Chaudhuri, Niraj K. Jha:
Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs. ACM J. Emerg. Technol. Comput. Syst. 12(4): 43:1-43:25 (2016)
[c4]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/ChaudhuriBBJ16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/ChaudhuriBBJ16
Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha:
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. VLSID 2016: 300-305
2014
[j2]
- view
  authority control:
- export record
  dblp key:
  - journals/jetc/ChaudhuriJ14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jetc/ChaudhuriJ14
Sourindra Chaudhuri, Niraj K. Jha:
3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations. ACM J. Emerg. Technol. Comput. Syst. 10(3): 26:1-26:19 (2014)
[j1]
- view
  authority control:
- export record
  dblp key:
  - journals/jetc/ChaudhuriMJ14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jetc/ChaudhuriMJ14
Sourindra M. Chaudhuri, Prateek Mishra, Niraj K. Jha:
Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology. ACM J. Emerg. Technol. Comput. Syst. 11(2): 19:1-19:20 (2014)
[c3]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/ChaudhuriJ14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/ChaudhuriJ14
Sourindra Chaudhuri, Niraj K. Jha:
FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. VLSID 2014: 476-482
2012
[c2]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/ChaudhuriMJ12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/ChaudhuriMJ12
Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha:
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. VLSI Design 2012: 238-244
2011
[c1]
- view
  authority control:
- export record
  dblp key:
  - conf/iccd/ChaudhuriJ11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccd/ChaudhuriJ11
Sourindra Chaudhuri, Niraj K. Jha:
3D vs. 2D analysis of FinFET logic gates under process variations. ICCD 2011: 435-436

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.