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Haoyuan Ying
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2010 – 2019
- 2015
- [b1]Haoyuan Ying:
A novel design and verification framework for low vertical link density 3D network-on-chip based many core embedded systems. Darmstadt University of Technology, 2015, pp. 1-173 - [c13]Thomas Hollstein
, Siavoosh Payandeh Azad
NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip. DDECS 2015: 75-78 - 2014
- [c12]Haoyuan Ying, Klaus Hofmann, Thomas Hollstein
Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips. HPCS 2014: 516-522 - [c11]Kris Heid, Haoyuan Ying, Christian Hochberger, Klaus Hofmann:
LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip. ReCoSoC 2014: 1-7 - [c10]Haoyuan Ying, Thomas Hollstein
A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method. ReCoSoC 2014: 1-8 - 2013
- [j1]Haoyuan Ying, Ashok Jaiswal, Thomas Hollstein
Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies. J. Syst. Archit. 59(7): 528-542 (2013) - [c9]Haoyuan Ying, Thomas Hollstein, Klaus Hofmann:
Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems. DATE 2013: 1777-1782 - [c8]Haoyuan Ying, Thomas Hollstein
GSNoC - The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems. HPCS 2013: 217-223 - 2012
- [c7]Haoyuan Ying, Ashok Jaiswal, Mohamed A. Abd El-Ghany
A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations. DDECS 2012: 83-88 - [c6]Philip Gottschling, Haoyuan Ying, Klaus Hofmann:
GSNOC UI - A comfortable graphical user interface for advanced design and evaluation of 3-dimensional scalable Networks-on-Chip. HPCS 2012: 261-267 - [c5]Haoyuan Ying, Ashok Jaiswal, Klaus Hofmann:
Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies. HPCS 2012: 268-274 - [c4]Haoyuan Ying, Kris Heid, Thomas Hollstein
A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems. NORCHIP 2012: 1-4 - [c3]Haoyuan Ying, Thomas Hollstein
Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip. ReCoSoC 2012: 1-6 - 2011
- [c2]Haoyuan Ying, Ashok Jaiswal, Thomas Hollstein
A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication. DSD 2011: 63-70 - [c1]Thomas Hollstein
Invited paper: Design criteria for dependable System-on-Chip architectures. ReCoSoC 2011: 1-6
Coauthor Index
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