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Zhe Jiang 0004
Person information
- affiliation: homepages/50/4629-4
- affiliation (former): University of York, UK
Other persons with the same name
- Zhe Jiang — disambiguation page
- Zhe Jiang 0001
— University of Florida, Gainesville, FL, USA (and 1 more)
- Zhe Jiang 0002
- Zhe Jiang 0003 — Beijing University of Posts & Telecommunications, Beijing, China
- Zhe Jiang 0005 — Academy of Mathematics and Systems Science, Chinese Academy of Science, Beijing, China
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2020 – today
- 2025
- [c27]Hui Wang, Yuan Cheng, Xiaomeng Han, Zhengpeng Zhao, Dawei Yang, Zhe Jiang:
Pushing the Limits of BFP on Narrow Precision LLM Inference. AAAI 2025: 21099-21107 - [i17]Xing Hu, Yuan Cheng, Dawei Yang, Zukang Xu, Zhihang Yuan, Jiangyong Yu, Chen Xu, Zhe Jiang, Sifan Zhou:
OstQuant: Refining Large Language Model Quantization with Orthogonal and Scaling Transformations for Better Distribution Fitting. CoRR abs/2501.13987 (2025) - [i16]Hui Wang, Yuan Cheng, Xiaomeng Han, Zhengpeng Zhao, Dawei Yang, Zhe Jiang:
Pushing the Limits of BFP on Narrow Precision LLM Inference. CoRR abs/2502.00026 (2025) - [i15]Hui Wang, Zhengpeng Zhao, Jing Wang, Yushu Du, Yuan Cheng, Bing Guo, He Xiao, Chenhao Ma, Xiaomeng Han, Dean You, Jiapeng Guan, Ran Wei, Dawei Yang, Zhe Jiang:
NVR: Vector Runahead on NPUs for Sparse Memory Access. CoRR abs/2502.13873 (2025) - [i14]Renshuang Jiang, Pan Dong, Zhenling Duan, Yu Shi, Xiaoxiang Fang, Yan Ding, Jun Ma, Shuai Zhao, Zhe Jiang:
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors. CoRR abs/2503.02335 (2025) - [i13]Jie Zhou, Youshu Ji, Ning Wang, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao, Nan Guan, Zhe Jiang:
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. CoRR abs/2503.04057 (2025) - [i12]Dean You, Jieyu Jiang, Xiaoxuan Wang, Yushu Du, Zhihang Tan, Wenbo Xu, Hui Wang, Jiapeng Guan, Zhenyuan Wang, Ran Wei, Shuai Zhao, Zhe Jiang:
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors. CoRR abs/2504.01582 (2025) - [i11]Yiyang Gao, Shuai Zhao, Boyang Li, Xinwei Fang, Zhiyang Lin, Zhe Jiang, Nan Guan:
Exploiting the Uncertainty of the Longest Paths: Response Time Analysis for Probabilistic DAG Tasks. CoRR abs/2504.03754 (2025) - [i10]Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang:
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback. CoRR abs/2504.15804 (2025) - [i9]Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang:
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. CoRR abs/2504.19099 (2025) - [i8]Junhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou, Shuai Zhao, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang:
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification. CoRR abs/2504.19959 (2025) - 2024
- [j19]Ran Wei
Towards an extensible model-based digital twin framework for space launch vehicles. J. Ind. Inf. Integr. 41: 100641 (2024) - [j18]Dawei Yang
Post-training quantization for re-parameterization via coarse & fine weight splitting. J. Syst. Archit. 147: 103065 (2024) - [j17]Dawei Yang, Yan Wang, Ran Wei, Jiapeng Guan, Xiaohua Huang, Wei Cai, Zhe Jiang
An efficient multi-task learning CNN for driver attention monitoring. J. Syst. Archit. 148: 103085 (2024) - [j16]Qingqiang He
On the degree of parallelism for parallel real-time tasks. J. Syst. Archit. 156: 103286 (2024) - [j15]Ran Wei
Automated Model-Based Assurance Case Management Using Constrained Natural Language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 291-304 (2024) - [j14]Ran Wei
DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1346-1359 (2024) - [j13]Zhe Jiang
Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs. IEEE Trans. Parallel Distributed Syst. 35(1): 89-104 (2024) - [c26]Yuchen Hu
Make Each Iteration Count. ACM TUR-C 2024 - [c25]Zhe Jiang
A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips. DAC 2024: 143:1-143:6 - [c24]Ke Xu
MEIC: Re-thinking RTL Debug Automation using LLMs. ICCAD 2024: 100:1-100:9 - [c23]Xiaoxiang Fang
Optimization of NUMA Aware DNN Computing System. ICIC (4) 2024: 124-136 - [c22]Leilei Li
Adaptive Optimisation of PyTorch Memory Pools for DNNs. PRICAI (1) 2024: 441-453 - [c21]Jiapeng Guan, Ran Wei, Dean You, Yingquan Wang, Ruizhe Yang, Hui Wang, Zhe Jiang:
MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs. RTSS 2024: 1-14 - [c20]Zhe Jiang, Shuai Zhao, Ran Wei, Xin Si, Gang Chen, Nan Guan
ROTA-I/O: Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness. RTSS 2024: 174-186 - [i7]Ran Wei, Ruizhe Yang, Shijun Liu, Chongsheng Fan, Rong Zhou, Zekun Wu, Haochi Wang, Yifan Cai, Zhe Jiang:
Towards an Extensible Model-Based Digital Twin Framework for Space Launch Vehicles. CoRR abs/2406.02222 (2024) - [i6]Ning Wang, Bingkun Yao, Jie Zhou, Xi Wang, Zhe Jiang, Nan Guan:
Large Language Model for Verilog Generation with Golden Code Feedback. CoRR abs/2407.18271 (2024) - [i5]Zhe Jiang, Shuai Zhao, Ran Wei, Xin Si, Gang Chen, Nan Guan:
Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness. CoRR abs/2409.14779 (2024) - [i4]Jiapeng Guan, Ran Wei, Dean You, Yingquan Wang, Ruizhe Yang, Hui Wang, Zhe Jiang:
MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs. CoRR abs/2409.14837 (2024) - [i3]Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan:
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog. CoRR abs/2409.15186 (2024) - [i2]Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang:
UVLLM: An Automated Universal RTL Verification Framework using LLMs. CoRR abs/2411.16238 (2024) - 2023
- [j12]Zhe Jiang
A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems. IEEE Trans. Computers 72(1): 29-42 (2023) - [j11]Zhe Jiang
Towards Hard Real-Time and Energy-Efficient Virtualization for Many-Core Embedded Systems. IEEE Trans. Computers 72(1): 111-126 (2023) - [j10]Zhe Jiang
AXI-IC$^{\mathrm{ RT}}$ RT : Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs. IEEE Trans. Computers 72(3): 786-799 (2023) - [j9]Zhe Jiang
NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4629-4642 (2023) - [c19]Zhe Jiang
Many-Core Real-Time Network-on-Chip I/O Systems for Reducing Contention and Enhancing Predictability. CPS-IoT Week Workshops 2023: 227-233 - [c18]Zhe Jiang, Nathan Fisher
BlueFace: Integrating an Accelerator into the Core's Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs. DAC 2023: 1-6 - [i1]Dawei Yang, Ning He, Xing Hu, Zhihang Yuan, Jiangyong Yu, Chen Xu, Zhe Jiang:
Post-Training Quantization for Re-parameterization via Coarse & Fine Weight Splitting. CoRR abs/2312.10588 (2023) - 2022
- [j8]Zhe Jiang
PSpSys: A time-predictable mixed-criticality system architecture based on ARM TrustZone. J. Syst. Archit. 123: 102368 (2022) - [j7]Qingling Zhao, Mengfei Qu, Bo Huang, Zhe Jiang, Haibo Zeng:
Schedulability analysis and stack size minimization for adaptive mixed criticality scheduling with semi-Clairvoyance and preemption thresholds. J. Syst. Archit. 124: 102383 (2022) - [j6]Zhe Jiang, Kecheng Yang, Nathan Fisher, Neil C. Audsley, Zheng Dong
Towards an energy-efficient quarter-clairvoyant mixed-criticality system. J. Syst. Archit. 130: 102683 (2022) - [j5]Zhe Jiang
BlueVisor: Time-Predictable Hardware Hypervisor for Many-Core Embedded Systems. IEEE Trans. Computers 71(9): 2205-2218 (2022) - [j4]Zhe Jiang
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2): 320-333 (2022) - [j3]Zhe Jiang
Bridging the Pragmatic Gaps for Mixed-Criticality Systems in the Automotive Industry. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1116-1129 (2022) - [c17]Ran Wei, Zhe Jiang, Xiaoran Guo, Haitao Mei, Athanasios Zolotas
Designing critical systems with iterative automated safety analysis. DAC 2022: 181-186 - [c16]Zhe Jiang, Kecheng Yang, Neil C. Audsley, Nathan Fisher, Weisong Shi, Zheng Dong
BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCs. DAC 2022: 1261-1266 - 2021
- [c15]Zhe Jiang, Kecheng Yang, Yunfeng Ma, Nathan Fisher, Neil C. Audsley, Zheng Dong
I/O-GUARD: Hardware/Software Co-Design for I/O Virtualization with Guaranteed Real-time Performance. DAC 2021: 1159-1164 - [c14]Yankai Wang, Dawei Yang, Wei Zhang, Zhe Jiang, Wenqiang Zhang:
Adaptable Ensemble Distillation. ICASSP 2021: 1675-1679 - [c13]Zhe Jiang, Neil C. Audsley, Dayu Shill, Kecheng Yang, Nathan Fisher, Zheng Dong:
Brief Industry Paper: AXI-InterconnectRT: Towards a Real-Time AXI-Interconnect for System-on-Chips. RTAS 2021: 437-440 - [c12]Pan Yang, Pan Dong, Zhe Jiang, Jintao Xia, Yan Ding:
Work-in-Progress: a static partition for shared cache in mixed-time-sensitive system with balanced performance. RTCSA 2021: 210-212 - [c11]Zhe Jiang, Xiaotian Dai, Neil C. Audsley:
HIART-MCS: High Resilience and Approximated Computing Architecture for Imprecise Mixed-Criticality Systems. RTSS 2021: 290-303 - 2020
- [j2]Pan Dong, Zhe Jiang, Alan Burns, Yan Ding, Jun Ma
Build real-time communication for hybrid dual-OS system. J. Syst. Archit. 107: 101774 (2020) - [c10]Shuai Zhao, Zhe Jiang, Xiaotian Dai
Timing-Accurate General-Purpose I/O for Multi- and Many-Core Systems: Scheduling and Hardware Support. DAC 2020: 1-6 - [c9]Dawei Yang, Xinlei Li, Xiaotian Dai
All In One Network for Driver Attention Monitoring. ICASSP 2020: 2258-2262 - [c8]Zhe Jiang, Shuai Zhao, Pan Dong, Dawei Yang, Ran Wei, Nan Guan
Re-Thinking Mixed-Criticality Architecture for Automotive Industry. ICCD 2020: 510-517 - [c7]Zhe Jiang, Kecheng Yang, Nathan Fisher, Neil C. Audsley, Zheng Dong
Pythia-MCS: Enabling Quarter-Clairvoyance in I/O-Driven Mixed-Criticality Systems. RTSS 2020: 38-50
2010 – 2019
- 2019
- [j1]Zhe Jiang
BlueIO: A Scalable Real-Time Hardware I/O Virtualization System for Many-core Embedded Systems. ACM Trans. Embed. Comput. Syst. 18(3): 19:1-19:25 (2019) - [c6]Zhe Jiang, Neil C. Audsley, Pan Dong, Nan Guan
MCS-IOV: Real-Time I/O Virtualization for Mixed-Criticality Systems. RTSS 2019: 326-338 - [c5]Pan Dong, Zhe Jiang, Alan Burns, Yan Ding, Jun Ma:
Work-in-Progress: Real-Time RPC for Hybrid Dual-OS System. RTSS 2019: 532-535 - 2018
- [b1]Zhe Jiang:
Real-time I/O system for many-core embedded systems. University of York, UK, 2018 - [c4]Zhe Jiang
BlueVisor: A Scalable Real-Time Hardware Hypervisor for Many-Core Embedded Systems. RTAS 2018: 75-84 - [c3]Pan Dong, Alan Burns, Zhe Jiang
TZDKS: A New TrustZone-Based Dual-Criticality System with Balanced Performance. RTCSA 2018: 59-64 - 2017
- [c2]Zhe Jiang
GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systems. DATE 2017: 806-811 - [c1]Zhe Jiang
VCDC: The Virtualized Complicated Device Controller. ECRTS 2017: 5:1-5:21
Coauthor Index
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last updated on 2025-05-27 21:53 CEST by the dblp team
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