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Edson I. Moreno
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2010 – 2019
- 2014
- [j3]Edson I. Moreno, Thais Webber
, César A. M. Marcon
MoNoC: A monitored network on chip with path adaptation mechanism. J. Syst. Archit. 60(10): 783-795 (2014) - [c9]Edson I. Moreno, Thais Webber
A monitored NoC with runtime path adaptation. ISCAS 2014: 1965-1968 - 2013
- [c8]Alexandre M. Amory
Determining the test sources/sinks for NoC TAMs. ISVLSI 2013: 8-13 - 2012
- [c7]Yan Ghidini, Thais Webber
Buffer depth and traffic influence on 3D NoCs performance. RSP 2012: 9-15 - [c6]Yan Ghidini, Thais Webber
Topological impact on latency and throughput: 2D versus 3D NoC comparison. SBCCI 2012: 1-6 - 2011
- [j2]César A. M. Marcon
CAFES: A framework for intrachip application modeling and communication architecture design. J. Parallel Distributed Comput. 71(5): 714-728 (2011) - [c5]Edson I. Moreno, César A. M. Marcon
Arbitration and routing impact on NoC design. International Symposium on Rapid System Prototyping 2011: 193-198 - 2010
- [b1]Edson Ifarraguirre Moreno:
Mapeamento e adaptação de rotas de comunicação em redes em chip. Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil, 2010
2000 – 2009
- 2008
- [j1]César Augusto Missio Marcon
Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Comput. Digit. Tech. 2(6): 471-482 (2008) - [c4]Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans
Integrating Abstract NoC Models within MPSoC Design. IEEE International Workshop on Rapid System Prototyping 2008: 65-71 - 2007
- [c3]César A. M. Marcon
Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS 2007: 389-392 - [i1]Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. CoRR abs/0710.4795 (2007) - 2005
- [c2]Alexandre M. Amory
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. DATE 2005: 62-63 - 2003
- [c1]Ney Laert Vilar Calazans
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI 2003: 355-
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