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Said Belkouch
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2020 – today
- 2022
- [j9]Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou
, Anas Hatim
Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. Comput. Electr. Eng. 102: 108294 (2022) - [c9]Noureddine Chabini, Said Belkouch, Mohamed Najoui:
An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs. ICECOCS 2022: 1-3 - 2021
- [j8]Abdessamad Klilou, Assia Arsalane
An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP. Microprocess. Microsystems 85: 104302 (2021) - 2020
- [j7]Mohamed Najoui
Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture. J. Circuits Syst. Comput. 29(12): 2050200:1-2050200:23 (2020) - [j6]Lhoussein Mabrouk, Sylvain Huet, Dominique Houzet, Said Belkouch, Abdelkrim Hamzaoui, Yahya Zennayi
Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU-GPU platforms. J. Real Time Image Process. 17(5): 1567-1583 (2020)
2010 – 2019
- 2018
- [c8]Lhoussein Mabrouk, Sylvain Huet, Dominique Houzet, Said Belkouch, Abdelkrim Hamzaoui, Yahya Zennayi
Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection. ATSIP 2018: 1-5 - [c7]Lhoussein Mabrouk, Dominique Houzet, Sylvain Huet, Said Belkouch, Abdelkrim Hamzaoui, Yahya Zennayi
Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection. CIST 2018: 308-312 - 2017
- [j5]Mohamed Najoui, Mounir Bahtat, Anas Hatim
VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing. J. Circuits Syst. Comput. 26(9): 1750129:1-1750129:26 (2017) - [c6]Mohamed Najoui, Anas Hatim
Novel parallel Givens QR decomposition implementation on VLIW architecture with Efficient memory access for real time image processing applications. BDCA 2017: 89:1-89:6 - 2016
- [j4]Mounir Bahtat
Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage. EURASIP J. Adv. Signal Process. 2016: 38 (2016) - [j3]Anas Hatim
Efficient architecture for direct 8 × 8 2D DCT computations with earlier zigzag ordering. Multim. Tools Appl. 75(11): 6121-6141 (2016) - 2015
- [c5]Noureddine Chabini, Said Belkouch:
Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders. AICCSA 2015: 1-4 - [c4]Abdessamad Klilou
Real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors. ISDA 2015: 183-188 - 2014
- [j2]Abdessamad Klilou
Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect. EURASIP J. Adv. Signal Process. 2014: 161 (2014) - [c3]Mounir Bahtat, Said Belkouch, Philippe Elleaume, Phillipe Le Gall:
Fast enumeration-based modulo scheduling heuristic for VLIW architectures. ICM 2014: 116-119 - 2013
- [j1]Anas Hatim
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications. Multim. Tools Appl. 67(3): 667-685 (2013)
2000 – 2009
- 2009
- [c2]Michael Guarisco, Hassan Rabah
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. SoCC 2009: 423-426 - 2007
- [c1]Ahmed El Oualkadi
A CMOS High-Q LC Eight-Path Bandpass Filter for Wireless Broadband Applications. ICECS 2007: 359-362
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