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Nadjia Anane
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2010 – 2019
- 2015
- [c7]Nadjia Anane, Mohamed Anane:
AES IP for hybrid cryptosystem RSA-AES. SSD 2015: 1-6 - [c6]Mohamed Anane, Nadjia Anane:
SHA-2 hardware core for virtex-5 FPGA. SSD 2015: 1-5 - 2014
- [j3]Mohamed Issad
, Bachir Boudraa
Software/Hardware Co-Design of Modular Exponentiation for Efficient RSA Cryptosystem. J. Circuits Syst. Comput. 23(3) (2014) - [c5]Nadjia Anane, Mohamed Anane:
High throughput parallel montgomery modular exponentiation on FPGA. IDT 2014: 225-230 - 2013
- [c4]Nadjia Anane, Mohamed Anane:
FPGA implementation of the m-ary modular exponentiation. IDT 2013: 1-2 - [c3]Mohamed Anane, Nadjia Anane:
High radix montgomery modular multiplication on FPGA. IDT 2013: 1-2 - 2011
- [j2]Mohamed Issad
An optimised architecture for radix-2 Montgomery modular multiplication on FPGA. Int. J. High Perform. Syst. Archit. 3(4): 175-183 (2011)
2000 – 2009
- 2009
- [c2]Nadjia Anane, Mohamed Anane, Hamid Bessalah, Mohamed Issad, Khadidja Messaoudi:
Hardware algorithm for variable precision multiplication on FPGA. AICCSA 2009: 845-848 - [c1]Mohamed Anane, Nadjia Anane, Hamid Bessalah, Mohamed Issad:
Reconfigurable architecture for elementary functions evaluation. AICCSA 2009: 853-856 - 2008
- [j1]Mohamed Anane, Hamid Bessalah, Mohamed Issad
Higher Radix and Redundancy Factor for Floating Point SRT Division. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 774-779 (2008)
Coauthor Index
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