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Masao Nakaya
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2000 – 2009
- 2008
- [j9]Masao Nakaya:
Special Section on Advanced Technologies in Digital LSIs and Memories. IEICE Trans. Electron. 91-C(4): 399 (2008) - 2007
- [j8]Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf:
Roundtable: Envisioning the Future for Multiprocessor SoC. IEEE Des. Test Comput. 24(2): 174-183 (2007) - 2000
- [j7]James C. Morizio
, Michael Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh
14-bit 2.2-MS/s sigma-delta ADC's. IEEE J. Solid State Circuits 35(7): 968-976 (2000) - [c4]James C. Morizio
SNDR sensitivity analysis for cascaded ΣΔ modulators. ISCAS 2000
1990 – 1999
- 1998
- [j6]Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya:
Software pipelining with path selection. Syst. Comput. Jpn. 29(9): 74-86 (1998) - 1996
- [c3]Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya:
Performance Comparison of ILP Machines with Cycle Time Evaluation. ISCA 1996: 213-224 - 1995
- [j5]Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya:
Code scheduling on a superscalar processor: SARCH. Syst. Comput. Jpn. 26(9): 13-22 (1995) - [c2]Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya:
Unconstrained Speculative Execution with Predicated State Buffering. ISCA 1995: 126-137 - 1993
- [j4]Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao, Masao Nakaya:
A VLSI chip set for a large-scale parallel inference machine: PIM/m. IEEE J. Solid State Circuits 28(3): 344-351 (1993) - [j3]Harufusa Kondoh
A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture. IEEE J. Solid State Circuits 28(7): 808-815 (1993) - [c1]Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya:
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. ICCD 1993: 106-113
1980 – 1989
- 1988
- [j2]Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba:
A DSP line equalizer VLSI for TCM digital subscriber-line transmission. IEEE J. Solid State Circuits 23(1): 118-123 (1988) - [j1]Toshio Kumamoto, Masao Nakaya, Shigeru Kusunoki, Tadashi Nishimura, Nobuharu Yazawa, Yoichi Akasaka, Yasutaka Horiba:
An SOI structure for flash A/D converter. IEEE J. Solid State Circuits 23(1): 198-201 (1988)
Coauthor Index
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