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Tobias Gemmeke
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2020 – today
- 2024
- [j18]Martin Lahr
, Johnson Loh
Vehicle Surroundings Perception Using Micro-electromechanical Systems Inertial Sensors. Adv. Intell. Syst. 6(5) (2024) - [j17]Thiago Santos Copetti
A DfT Strategy for Guaranteeing ReRAM's Quality after Manufacturing. J. Electron. Test. 40(2): 245-257 (2024) - [j16]Jie Lou
An Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 287-298 (2024) - [j15]Daniel Fallnich, Christian Lanius, Shutao Zhang, Tobias Gemmeke:
Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 403-425 (2024) - [j14]Christian Lanius
Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 30-41 (2024) - [j13]Johnson Loh
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 68-78 (2024) - [c47]Kevin Kauth, Christian Lanius, Tobias Gemmeke:
nAIxt: A Light-Weight Processor Architecture for Efficient Computation of Neuron Models. ARCS 2024: 3-17 - [c46]Florian Freye, Jie Lou, Christian Lanius, Tobias Gemmeke:
Merits of Time-Domain Computing for VMM - A Quantitative Comparison. ISQED 2024: 1-8 - [i5]Florian Freye, Jie Lou, Christian Lanius, Tobias Gemmeke:
Merits of Time-Domain Computing for VMM - A Quantitative Comparison. CoRR abs/2403.18367 (2024) - 2023
- [j12]Kevin Kauth, Tim Stadtmann, Vida Sobhani
neuroAIx-Framework: design of future neuroscience simulation systems exhibiting execution of the cortical microcircuit model 20× faster than biological real-time. Frontiers Comput. Neurosci. 17 (2023) - [j11]Ugo Bruno
From neuromorphic to neurohybrid: transition from the emulation to the integration of neuronal networks. Neuromorph. Comput. Eng. 3(2): 23002 (2023) - [c45]Shutao Zhang, Malte Wabnitz, Tobias Gemmeke:
A Compact 1,257-Gbps/W Byte-Serial AES Accelerator for IoT Applications in 22 nm. A-SSCC 2023: 1-3 - [c44]Johnson Loh, Tobias Gemmeke:
Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous Signals. DATE 2023: 1-6 - [c43]Shutao Zhang, Tobias Gemmeke:
A 22-nm 1,287-MOPS/W Structured Data-Path Array for Binary Ring-LWE PQC. ESSCIRC 2023: 189-192 - [c42]Jie Lou
Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices. ACM Great Lakes Symposium on VLSI 2023: 665-670 - [c41]Tim Stadtmann, Benedikt Wahl, Tobias Gemmeke:
NoisyDECOLLE: Robust Local Learning for SNNs on Neuromorphic Hardware. ICMLA 2023: 1535-1540 - [c40]Christian Lanius, Florian Freye, Shutao Zhang, Tobias Gemmeke:
Hardware Trojans in fdSOI. ISLPED 2023: 1-6 - [c39]Christian Lanius, Jie Lou, Johnson Loh, Tobias Gemmeke:
Automatic Generation of Structured Macros Using Standard Cells ‒ Application to CIM. ISLPED 2023: 1-6 - [c38]Cecilia Latotzke, Amarin Kloeker, Simon Schoening, Fabian Kemper, Mazen Slimi, Lutz Eckstein, Tobias Gemmeke:
FPGA-based Acceleration of Lidar Point Cloud Processing and Detection on the Edge. IV 2023: 1-8 - [c37]Thiago Santos Copetti, A. Castelnuovo, Tobias Gemmeke, Letícia Maria Veiras Bolzani:
Evaluating a New RRAM Manufacturing Test Strategy. LATS 2023: 1-6 - [c36]Kevin Kauth, Tim Stadtmann, Vida Sobhani
neuroAIx: FPGA Cluster for Reproducible and Accelerated Neuroscience Simulations of SNNs. NorCAS 2023: 1-7 - [c35]Mikail Yayla
DAEBI: A Tool for Data Flow and Architecture Explorations of Binary Neural Network Accelerators. SAMOS 2023: 107-122 - [c34]Yi Chen, Jie Lou, Christian Lanius, Florian Freye, Johnson Loh, Tobias Gemmeke:
An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access. VLSI-SoC 2023: 1-6 - [c33]Vida Sobhani
A Digital Twin Network for Computational Neuroscience Simulators: Exploring Network Architectures for Acceleration of Biological Neural Network Simulations. WoWMoM 2023: 483-488 - 2022
- [j10]Vida Sobhani
Deadlock-Freedom in Computational Neuroscience Simulators. IEEE Des. Test 39(6): 70-78 (2022) - [j9]Xin Fan
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2560-2572 (2022) - [c32]Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE 2022: 957-962 - [c31]Jie Lou, Christian Lanius, Florian Freye, Tim Stadtmann, Tobias Gemmeke
All-Digital Time-Domain Compute-in-Memory Engine for Binary Neural Networks With 1.05 POPS/W Energy Efficiency. ESSCIRC 2022: 149-152 - [c30]Cecilia Latotzke, Tim Ciesielski, Tobias Gemmeke
Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA. FPL 2022: 358-365 - [c29]Cecilia Latotzke, Batuhan Balim, Tobias Gemmeke:
Post-Training Quantization for Energy Efficient Realization of Deep Neural Networks. ICMLA 2022: 1559-1566 - [c28]Michael Gansen, Jie Lou, Florian Freye
Discrete Steps towards Approximate Computing. ISQED 2022: 1-6 - [c27]Thiago Santos Copetti, M. Nilovic, Moritz Fieback
Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs. LATS 2022: 1-6 - [c26]Christian Lanius
Multi-Function CIM Array for Genome Alignment Applications built with Fully Digital Flow. NorCAS 2022: 1-7 - [c25]Johnson Loh, Tobias Gemmeke
Dataflow Optimizations in a Sub-uW Data-Driven TCN Accelerator for Continuous ECG Monitoring. NorCAS 2022: 1-7 - [i4]Cecilia Latotzke, Tim Ciesielski, Tobias Gemmeke
Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA. CoRR abs/2208.04854 (2022) - [i3]Cecilia Latotzke, Batuhan Balim, Tobias Gemmeke
Post-Training Quantization for Energy Efficient Realization of Deep Neural Networks. CoRR abs/2210.07906 (2022) - [i2]Daniel Fallnich, Shutao Zhang, Tobias Gemmeke
Efficient ASIC Architectures for Low Latency Niederreiter Decryption. IACR Cryptol. ePrint Arch. 2022: 469 (2022) - 2021
- [j8]Cecilia Latotzke
Efficiency Versus Accuracy: A Review of Design Techniques for DNN Hardware Accelerators. IEEE Access 9: 9785-9799 (2021) - [j7]Letícia Maria Veiras Bolzani
Review of Manufacturing Process Defects and Their Effects on Memristive Devices. J. Electron. Test. 37(4): 427-437 (2021) - [c24]Cecilia Latotzke
Cascaded Classifier for Pareto-Optimal Accuracy-Cost Trade-Off Using Off-the-Shelf ANNs. LOD 2021: 423-435 - [c23]Thiago Santos Copetti, Tobias Gemmeke
Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs. VLSI-SoC 2021: 1-6 - [c22]Thiago Santos Copetti, Tobias Gemmeke
A DfT Strategy for Detecting Emerging Faults in RRAMs. VLSI-SoC (Selected Papers) 2021: 93-111 - [i1]Cecilia Latotzke, Johnson Loh, Tobias Gemmeke:
Cascaded Classifier for Pareto-Optimal Accuracy-Cost Trade-Off Using off-the-Shelf ANNs. CoRR abs/2110.14256 (2021) - 2020
- [j6]Xin Fan
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2495-2508 (2020) - [c21]Johnson Loh, Jianan Wen
Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection. ASAP 2020: 213-216 - [c20]Tim Stadtmann, Cecilia Latotzke, Tobias Gemmeke
From Quantitative Analysis to Synthesis of Efficient Binary Neural Networks. ICMLA 2020: 93-100 - [c19]Kevin Kauth, Tim Stadtmann, Ruben Brandhofer, Vida Sobhani
Communication architecture enabling 100x accelerated simulation of biological neural networks. SLIP 2020: 2
2010 – 2019
- 2019
- [j5]Xin Fan
Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 941-954 (2019) - 2018
- [c18]Rubén Salvador, Alberto Sanchez, Xin Fan, Tobias Gemmeke
A Cortex-M3 Based MCV Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature. ESSCIRC 2018: 278-281 - [c17]Xin Fan, Rui Wang, Tobias Gemmeke
Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations. ICCAD 2018: 38 - 2017
- [j4]Georgia Psychou
Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems. ACM Comput. Surv. 50(4): 50:1-50:38 (2017) - [c16]Xin Fan, Jan Stuijt, Tobias Gemmeke
Towards SRAM leakage power minimization by aggressive standby voltage scaling - Experiments on 40nm test chips. DFT 2017: 1-4 - [c15]Xin Fan, Jan Stuijt, Rui Wang, Bo Liu, Tobias Gemmeke
Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations. ISQED 2017: 65-70 - 2016
- [c14]Daniele Bortolotti
PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms. Conf. Computing Frontiers 2016: 309-314 - [c13]Georgia Psychou, Tobias Gemmeke
A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects. PATMOS 2016: 147-154 - [p1]Tobias Gemmeke
Memories for NTC. Near Threshold Computing 2016: 75-100 - 2015
- [c12]Georgia Psychou, Tobias Gemmeke
On the use of analytical techniques for reliability analysis in presence of hardware-induced errors. INDIN 2015: 1416-1423 - 2014
- [c11]Tobias Gemmeke
Resolving the memory bottleneck for single supply near-threshold computing. DATE 2014: 1-6 - [c10]Bo Liu, Maryam Ashouei, Tobias Gemmeke
Sub-threshold custom standard cell library validation. ISQED 2014: 257-262 - [c9]Christian Bachmann
10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks. ISSCC 2014: 186-187 - 2013
- [c8]Tobias Gemmeke
In-situ performance monitor employing threshold based notifications (TheBaN). ESSCIRC 2013: 271-274 - [c7]Mario Konijnenburg, Yeon-Gon Cho, Maryam Ashouei, Tobias Gemmeke, Changmoo Kim, Jos Hulzink, Jan Stuyt, Mookyung Jung, Jos Huisken, Soojung Ryu, Jungwook Kim, Harmke de Groot:
Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS. ISSCC 2013: 430-431 - 2012
- [c6]Tobias Gemmeke
Variability aware cell library optimization for reliable sub-threshold operation. ESSCIRC 2012: 42-45 - [c5]Tobias Gemmeke
Noise Margin Based Library Optimization Considering Variability in Sub-threshold. PATMOS 2012: 72-82
2000 – 2009
- 2007
- [j3]Joachim Fenkes, Tobias Gemmeke
Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. J. Low Power Electron. 3(1): 54-59 (2007) - 2005
- [c4]Gordian Prescher, Tobias Gemmeke
A parametrizable low-power high-throughput turbo-decoder. ICASSP (5) 2005: 25-28 - 2004
- [j2]Tobias Gemmeke
Design optimization of low-power high-performance DSP building blocks. IEEE J. Solid State Circuits 39(7): 1131-1139 (2004) - [c3]Tobias Gemmeke, Tobias G. Noll:
A physically oriented model to quantify the dynamic noise margin [on-chip noise]. ESSCIRC 2004: 467-470 - [c2]Tobias Gemmeke
A Physically Oriented Model to Quantify the Noise-on-Delay Effect. PATMOS 2004: 879-888 - 2003
- [c1]Tobias Gemmeke
Optimization of device dimensions for high-performance low-power architecture blocks. ESSCIRC 2003: 305-308 - 2002
- [j1]Tobias Gemmeke
Implementation of scalable power and area efficient high-throughput Viterbi decoders. IEEE J. Solid State Circuits 37(7): 941-948 (2002)
Coauthor Index
Letícia Maria Veiras Bolzani
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
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last updated on 2024-10-07 21:11 CEST by the dblp team
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