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João Canas Ferreira
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2020 – today
- 2021
- [j23]Nuno Paulino
, João Canas Ferreira
Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey. ACM Comput. Surv. 53(1): 6:1-6:36 (2021) - [j22]Nuno Paulino
A Binary Translation Framework for Automated Hardware Generation. IEEE Micro 41(4): 15-23 (2021) - [c41]Tiago Santos
On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. FPT 2021: 1-4 - [i1]Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo:
A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. CoRR abs/2112.01875 (2021) - 2020
- [j21]Leonardo Alves Dias
Parallel Implementation of K-Means Algorithm on FPGA. IEEE Access 8: 41071-41084 (2020) - [j20]Nuno Paulino
Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets. IEEE Access 8: 152286-152304 (2020) - [j19]Fardin Derogarian
A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems. IEEE/ACM Trans. Netw. 28(5): 1981-1994 (2020) - [j18]Mário Lopes Ferreira
A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications. J. Signal Process. Syst. 92(4): 409-424 (2020) - [c40]Guilherme Carvalho
Hardware architecture for integrate-and-fire signal reconstruction on FPGA. DCIS 2020: 1-6 - [c39]Nuno Paulino
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. FPL 2020: 367
2010 – 2019
- 2019
- [j17]Nuno Miguel Cardanha Paulino
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 116-125 (2019) - [j16]João Canas Ferreira
Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing. J. Signal Process. Syst. 91(7): 701-702 (2019) - 2018
- [j15]Fardin Derogarian, João Canas Ferreira
Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding. J. Mobile Multimedia 14(4): 469-504 (2018) - [j14]Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem. Microprocess. Microsystems 58: 1-12 (2018) - [c38]Mário Lopes Ferreira
A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems. ARC 2018: 511-522 - [c37]Helder H. Avelar, João Canas Ferreira
Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing. DSD 2018: 488-491 - [c36]Mário Lopes Ferreira
Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator. ISCAS 2018: 1-5 - 2017
- [j13]João Canas Ferreira
MICPRO DSD 2015 special issue. Microprocess. Microsystems 52: 438 (2017) - [j12]Nuno Miguel Cardanha Paulino
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 21-34 (2017) - [c35]Miguel Carvalho, Mário Lopes Ferreira
FPGA-based implementation of a frequency spreading FBMC-OQAM baseband modulator. ICECS 2017: 174-177 - [c34]Benedikt Janßen, Fatih Korkmaz, Halil Derya, Michael Hübner, Mário Lopes Ferreira
Towards a type 0 hypervisor for dynamic reconfigurable systems. ReConFig 2017: 1-7 - [c33]Joao Lopes, Diogo Sousa, João Canas Ferreira
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices. ReConFig 2017: 1-7 - 2016
- [j11]Fardin Derogarian, João Canas Ferreira
A small fully digital open-loop clock and data recovery circuit for wired BANs. Int. J. Circuit Theory Appl. 44(3): 530-548 (2016) - [j10]Pedro Miguel Salgueiro dos Santos
Scalable hardware architecture for disparity map computation and object location in real-time. J. Real Time Image Process. 11(3): 473-485 (2016) - [c32]Mário Lopes Ferreira
Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications. ARC 2016: 223-232 - [c31]Mário Lopes Ferreira
Dynamically reconfigurable FFT processor for flexible OFDM baseband processing. DTIS 2016: 1-6 - [c30]João Canas Ferreira
An FPGA implementation of a long short-term memory neural network. ReConFig 2016: 1-8 - 2015
- [j9]Fardin Derogarian, João Canas Ferreira
A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks. Microprocess. Microsystems 39(8): 1029-1038 (2015) - [j8]Nuno Miguel Cardanha Paulino
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. ACM Trans. Reconfigurable Technol. Syst. 7(4): 29:1-29:20 (2015) - [c29]Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso:
Transparent acceleration of program execution using reconfigurable hardware. DATE 2015: 1066-1071 - [c28]Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem. DSD 2015: 9-16 - [c27]Mário Lopes Ferreira
Reconfigurable NC-OFDM Processor for 5G Communications. EUC 2015: 199-204 - 2014
- [c26]Fardin Derogarian, João Canas Ferreira
A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks. DSD 2014: 146-153 - [c25]Fardin Derogarian, João Canas Ferreira
Design and implementation of hybrid circuit/packet switching for wearable systems. ISIE 2014: 1123-1128 - [c24]Nuno Miguel Cardanha Paulino
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. ISPA 2014: 158-165 - 2013
- [j7]João Bispo
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. Int. J. Reconfigurable Comput. 2013: 340316:1-340316:20 (2013) - [j6]José Machado da Silva
Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011). Microelectron. J. 44(10): 869 (2013) - [j5]João Bispo
Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. IEEE Trans. Ind. Informatics 9(3): 1625-1634 (2013) - [c23]Nuno Miguel Cardanha Paulino
Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. ARC 2013: 122-133 - [c22]Filipe Sousa, Francis Anghinolfi, João Canas Ferreira
Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques. DSD 2013: 829-835 - [c21]Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio. FPL 2013: 1-4 - 2012
- [j4]Miguel Lino Silva, João Canas Ferreira
Run-time generation of partial FPGA configurations. J. Syst. Archit. 58(1): 24-37 (2012) - [j3]Miguel Lino Silva, João Canas Ferreira
Run-time generation of partial FPGA configurations for subword operations. Microprocess. Microsystems 36(5): 365-374 (2012) - [c20]Ali Azarian
Analysis of error detection schemes: Toolchain support and hardware/software implications. AHS 2012: 62-69 - [c19]Fardin Derogarian, João Canas Ferreira
Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks. DSD 2012: 896-901 - [c18]Andreina Zambrano, Fardin Derogarian, Ruben Dias, Maria José Abreu
A Wearable Sensor Network for Human Locomotion Data Capture. pHealth 2012: 216-223 - [c17]Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
A scalable array for Cellular Genetic Algorithms: TSP as case study. ReConFig 2012: 1-6 - 2011
- [c16]João Bispo
From Instruction Traces to Specialized Reconfigurable Arrays. ReConFig 2011: 386-391 - 2010
- [c15]João G. P. Rodrigues, João Canas Ferreira
FPGA-based rectification of stereo images. DASIP 2010: 199-206 - [c14]Miguel Lino Silva, João Canas Ferreira
Creation of Partial FPGA Configurations at Run-Time. DSD 2010: 80-87 - [c13]Paulo Ferreira
Erlang Inspired Hardware. FPL 2010: 244-246
2000 – 2009
- 2008
- [c12]Miguel Lino Silva, João Canas Ferreira
Generation of partial FPGA configurations at run-time. FPL 2008: 367-372 - 2007
- [j2]Miguel Lino Silva, João Canas Ferreira
Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems. IET Comput. Digit. Tech. 1(5): 461-471 (2007) - 2006
- [j1]Miguel Lino Silva, João Canas Ferreira
Support for partial run-time reconfiguration of platform FPGAs. J. Syst. Archit. 52(12): 709-726 (2006) - [c11]Miguel L. Silva, João Canas Ferreira
Exploiting dynamic reconfiguration of platform FPGAs: implementation issues. IPDPS 2006 - 2005
- [c10]Miguel Lino Silva, João Canas Ferreira
Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. DSD 2005: 383-387 - [c9]João Canas Ferreira
Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer. IPDPS 2005 - 2004
- [c8]João Canas Ferreira, José Silva Matos:
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. FPL 2004: 886-890
1990 – 1999
- 1999
- [c7]José Carlos Alves, João Canas Ferreira
FAFNER-Accelerating Nesting Problems with FPGAs. FCCM 1999: 168- - 1998
- [c6]João Canas Ferreira
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. FCCM 1998: 280-281 - [c5]João Canas Ferreira
Mixed hardware/software applications on dynamically reconfigurable hardware. ICECS 1998: 97-100 - [c4]João Canas Ferreira
Flexible hardware acceleration for nesting problems. ICECS 1998: 345-348 - 1994
- [c3]José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva:
An Approach to Testability Improvement of Mixed-Signal Boards. ISCAS 1994: 161-164 - [c2]José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva:
Architecture of test support ICs for mixed-signal testing. VTS 1994: 240-246 - 1993
- [c1]José Silva Matos, Ana C. Leão, João Canas Ferreira:
Control and Observation of Analog Nodes in Mixed-Signal Boards. ITC 1993: 323-331
Coauthor Index
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