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Dhruva R. Chakrabarti

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affiliation: Hewlett Packard Enterprise Labs, Palo Alto, CA, USA

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2020 – today

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2024
[c31]
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Jan-Patrick Lehr, Michael Halkenhäuser, Dhruva R. Chakrabarti, Saiyedul Islam, Dan Palermo, Ron Lieberman:
ompTest - Unit Testing with OMPT. SC Workshops 2024: 196-203
[c30]
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Jan-Patrick Lehr, Michael Halkenhäuser, Dhruva R. Chakrabarti, Saiyedul Islam, Dan Palermo, Ron Lieberman:
OMPTBench - OpenMP Tool Interface Conformance Testing. SC Workshops 2024: 232-236
[c29]
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Carlo Bertolli, Thorsten Blass, Lynd Stringer, Nicole Aschenbrenner, Jan-Patrick Lehr, Doru Bercea, Dhruva R. Chakrabarti, Lawrence Meadows, Ron Lieberman:
Performance Analysis of Runtime Handling of Zero-Copy for OpenMP Programs on MI300A APUs. SC Workshops 2024: 1420-1429
2023
[c28]
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Dhruva R. Chakrabarti, Gregory Rodgers, Carlo Bertolli, Gheorghe-Teodor Bercea, Jan-Patrick Lehr, Lynd Stringer, Jan Leyonberg, Dan Palermo, Ron Lieberman:
Specialized Kernels for Optimizing GPU Offload in OpenMP. SC Workshops 2023: 1918-1928

2010 – 2019

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2017
[c27]
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Pengcheng Li, Dhruva R. Chakrabarti, Chen Ding, Liang Yuan:
Adaptive Software Caching for Efficient NVRAM Data Persistence. IPDPS 2017: 112-122
[c26]
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Faisal Nawab, Joseph Izraelevitz, Terence Kelly, Charles B. Morrey III, Dhruva R. Chakrabarti, Michael L. Scott:
Dalí: A Periodically Persistent Hash Map. DISC 2017: 37:1-37:16
2016
[c25]
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Hans-Juergen Boehm, Dhruva R. Chakrabarti:
Persistence programming models for non-volatile memory. ISMM 2016: 55-67
[c24]
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Pengcheng Li, Dhruva R. Chakrabarti:
Adaptive Software Caching for Efficient NVRAM Data Persistence. LCPC 2016: 93-97
[c23]
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Kumud Bhandari, Dhruva R. Chakrabarti, Hans-Juergen Boehm:
Makalu: fast recoverable allocation of non-volatile memory. OOPSLA 2016: 677-694
2015
[c22]
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Faisal Nawab, Dhruva R. Chakrabarti, Terence Kelly, Charles B. Morrey III:
Procrastination Beats Prevention: Timely Sufficient Persistence for Efficient Crash Resilience. EDBT 2015: 689-694
2014
[c21]
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Dhruva R. Chakrabarti, Hans-Juergen Boehm, Kumud Bhandari:
Atlas: leveraging locks for non-volatile memory consistency. OOPSLA 2014: 433-452
2013
[c20]
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Dhruva R. Chakrabarti, Hans-Juergen Boehm:
Durability Semantics for Lock-based Multithreaded Programs. HotPar 2013
2012
[j3]
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Pramod G. Joisha, Robert S. Schreiber, Prithviraj Banerjee, Hans-Juergen Boehm, Dhruva R. Chakrabarti:
On a Technique for Transparently Empowering Classical Compiler Optimizations on Multithreaded Code. ACM Trans. Program. Lang. Syst. 34(2): 9:1-9:42 (2012)
2011
[c19]
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Dhruva R. Chakrabarti, Prithviraj Banerjee, Hans-Juergen Boehm, Pramod G. Joisha, Robert S. Schreiber:
The runtime abort graph and its application to software transactional memory optimization. CGO 2011: 42-53
[c18]
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Laura Effinger-Dean, Hans-Juergen Boehm, Dhruva R. Chakrabarti, Pramod G. Joisha:
Extended sequential reasoning for data-race-free programs. MSPC 2011: 22-29
[c17]
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Pramod G. Joisha, Robert S. Schreiber, Prithviraj Banerjee, Hans-Juergen Boehm, Dhruva R. Chakrabarti:
A technique for the effective and automatic reuse of classical compiler optimizations on multithreaded code. POPL 2011: 623-636
2010
[c16]
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  - conf/iiswc/ChungCM10
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JaeWoong Chung, Dhruva R. Chakrabarti, Chi Cao Minh:
Analysis on semantic transactional memory footprint for hardware transactional memory. IISWC 2010: 1-11
[c15]
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Sandya Mannarswamy, Dhruva R. Chakrabarti, Kaushik Rajan, Sujoy Saraswati:
Compiler aided selective lock assignment for improving the performance of software transactional memory. PPoPP 2010: 37-46
[c14]
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Dhruva R. Chakrabarti:
New abstractions for effective performance analysis of STM programs. PPoPP 2010: 333-334

2000 – 2009

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2009
[c13]
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Seung Woo Son, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti:
A compiler-directed data prefetching scheme for chip multiprocessors. PPoPP 2009: 209-218
2006
[c12]
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Dhruva R. Chakrabarti, Shin-Ming Liu:
Inline Analysis: Beyond Selection Heuristics. CGO 2006: 221-232
[c11]
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Robert Hundt, Sandya Mannarswamy, Dhruva R. Chakrabarti:
Practical Structure Layout Optimization and Advice. CGO 2006: 233-244
2004
[c10]
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Dhruva R. Chakrabarti, Luis A. Lozano, Xinliang D. Li, Robert Hundt, Shin-Ming Liu:
Scalable High Performance Cross-Module Inlining. IEEE PACT 2004: 165-176
[c9]
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Sungdo Moon, Xinliang D. Li, Robert Hundt, Dhruva R. Chakrabarti, Luis A. Lozano, Uma Srinivasan, Shin-Ming Liu:
SYZYGY - A Framework for Scalable Cross-Module IPO. CGO 2004: 65-74
2001
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Dhruva R. Chakrabarti, Prithviraj Banerjee:
Static Single Assignment Form for Message-Passing Programs. Int. J. Parallel Program. 29(2): 139-184 (2001)
[c8]
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Dhruva R. Chakrabarti, Prithviraj Banerjee:
Global optimization techniques for automatic parallelization of hybrid applications. ICS 2001: 166-180
2000
[j1]
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Antonio Lain, Dhruva R. Chakrabarti, Prithviraj Banerjee:
Compiler and Run-Time Support for Exploiting Regularity within Irregular Applications. IEEE Trans. Parallel Distributed Syst. 11(2): 119-135 (2000)

1990 – 1999

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1999
[c7]
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Dhruva R. Chakrabarti, Prithviraj Banerjee:
A Novel Compilation Framework for Supporting Semi-Regular Distributions in Hybrid Applications. IPPS/SPDP 1999: 597-602
[c6]
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Dhruva R. Chakrabarti, Prithviraj Banerjee:
Accurate Data and Context Management in Message-Passing Programs. LCPC 1999: 117-132
1998
[c5]
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Dhruva R. Chakrabarti, Pramod G. Joisha, John A. Chandy, Krishnaswamy Krishnaswamy, Venkatram Krishnaswamy, Prithviraj Banerjee:
WADE: a Web-based automated parallel CAD environment. HiPC 1998: 473-480
[c4]
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Dhruva R. Chakrabarti, U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee:
An Efficient Uniform Run-time Scheme for Mixed Regular-irregular Applications. International Conference on Supercomputing 1998: 61-68
[c3]
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Dhruva R. Chakrabarti, Prithviraj Banerjee, Antonio Lain:
Evaluation of Compiler and Runtime Library Approaches for Supporting Parallel Regular Applications. IPPS/SPDP 1998: 74-79
1996
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Dhruva R. Chakrabarti, Ajai Jain:
An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits. VLSI Design 1996: 174-177
1995
[c1]
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Dhruva R. Chakrabarti, Ajai Jain:
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. Asian Test Symposium 1995: 237-243

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