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Saeed-ur Rehman

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2014
[b1]
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  - electronic edition @ archives-ouvertes.fr (open access)
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Saeed-ur Rehman:
Designing Optimized parallel interleaver architecture for Turbo and LDPC decoders. (Conception d'architectures d'entrelaceurs parallèles pour les décodeurs de Turbo-Codes et de LDPC). University of Southern Brittany, Morbihan, France, 2014
[c3]
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Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy:
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. ICASSP 2014: 5036-5040
2013
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Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet:
On-chip implementation of memory mapping algorithm to support flexible decoder architecture. ICASSP 2013: 2751-2755
2012
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Muhammad Rafiq Mufti, Saeed-ur Rehman, Fazal-ur Rehman, Qarab Raza Butt, Irfan Awan:
A second order sliding mode control design of a switched reluctance motor using super twisting algorithm. Simul. Model. Pract. Theory 25: 106-117 (2012)
[c1]
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  - conf/sips/SanchezJRSCCJ12
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Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo:
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS 2012: 288-293

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