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Yoshihide Komatsu
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2020 – today
- 2021
- [c4]Yasunori Tateno, Ken Nakata, Akio Oya, Keita Matsuda, Yoshihide Komatsu, Shinichi Osada, Masafumi Hirata, Shigeyuki Ishiyama, Toshiki Yoda, Atsushi Nitta, Tomio Sato:
Investigation of the Failure Mechanism of InGaAs-pHEMT under High Temperature Operating Life Tests. IRPS 2021: 1-4 - 2020
- [j8]Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata
:
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. 103-C(10): 497-504 (2020)
2010 – 2019
- 2019
- [j7]Yoshihide Komatsu
A 0.25-27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis. IEEE J. Solid State Circuits 54(10): 2802-2811 (2019) - 2018
- [c3]Yoshihide Komatsu, Akinori Shinmyo, Masami Funabashi, Shuji Kato, Kazuya Hatooka, Kenji Tanaka, Mayuko Fujita, Kouichi Fukuda:
A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K System. A-SSCC 2018: 63-66 - 2011
- [j6]Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa:
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration. IEEE J. Solid State Circuits 46(4): 986-991 (2011)
2000 – 2009
- 2009
- [j5]Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa:
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. IEEE J. Solid State Circuits 44(3): 763-774 (2009) - 2008
- [j4]Takefumi Yoshikawa, Yoshihide Komatsu, Tsuyoshi Ebuchi, Takashi Hirata:
Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces. IEICE Trans. Electron. 91-C(9): 1444-1452 (2008) - 2007
- [j3]Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Trans. Electron. 90-C(4): 692-698 (2007) - 2006
- [j2]Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada:
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 250-262 (2006) - [j1]Yoshihide Komatsu, Yukio Arima, Koichiro Ishibashi:
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 384-391 (2006) - 2005
- [c2]Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. CICC 2005: 35-38 - 2004
- [c1]Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi:
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. CICC 2004: 329-332
Coauthor Index
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