A 1.2V 23nm 6F\(^2\) 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture - Kyu-Nam Lim; Woong-Ju Jang; Hyung-Sik Won; Kang-Yeol Lee; Hyungsoo Kim; Dong-Whee Kim; Mi-Hyun Cho; Seung-Lo Kim; Jong-Ho Kang; Keun-Woo Park; Byung-Tae Jeong (2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, 2012)

A bitline sense amplifier for offset compensation - Myoung Jin Lee; Ki Myung Kyung; Hyung-Sik Won; Myoung Su Lee; Kun Woo Park (IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, 2010)