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Sotirios G. Ziavras
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- affiliation: New Jersey Institute of Technology, Department of Electrical and Computer Engineering, Newark, USA
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2020 – today
- 2020
- [j52]William Contreras
, Sotirios G. Ziavras
Low-Cost, Efficient Output-Only Infrastructure Damage Detection With Wireless Sensor Networks. IEEE Trans. Syst. Man Cybern. Syst. 50(3): 1003-1012 (2020)
2010 – 2019
- 2017
- [j51]Yaojie Lu, Sotirios G. Ziavras:
Instruction Fusion for Multiscalar and Many-Core Processors. Int. J. Parallel Program. 45(1): 67-78 (2017) - [c59]William Contreras, Sotirios G. Ziavras:
Efficient infrastructure damage detection and localization using wireless sensor networks, with cluster generation for monitoring damage progression. UEMCON 2017: 173-178 - [c58]William Contreras, Sotirios G. Ziavras:
Efficient structural health monitoring with wireless sensor networks using a vibration-based frequency domain pattern matching technique. UEMCON 2017: 356-362 - 2016
- [j50]William Contreras, Sotirios G. Ziavras:
Wireless sensor network-based pattern matching technique for the circumvention of environmental and stimuli-related variability in structural health monitoring. IET Wirel. Sens. Syst. 6(1): 26-33 (2016) - [j49]Yaojie Lu, Seyed A. Rooholamin, Sotirios G. Ziavras:
Vector Coprocessor Virtualization for Simultaneous Multithreading. ACM Trans. Embed. Comput. Syst. 15(3): 57:1-57:25 (2016) - [c57]Yaojie Lu, Seyed Amin Rooholamin, Sotirios G. Ziavras:
Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration. ISVLSI 2016: 81-86 - [c56]William Contreras, Sotirios G. Ziavras:
Wireless sensor network-based infrastructure damage detection constrained by energy consumption. UEMCON 2016: 1-7 - 2015
- [j48]Xiaofang Wang, Sotirios G. Ziavras
A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies. Int. J. Comput. Sci. Eng. 10(1/2): 181-191 (2015) - [j47]Seyed A. Rooholamin, Sotirios G. Ziavras
Modular vector processor architecture targeting at data-level parallelism. Microprocess. Microsystems 39(4-5): 237-249 (2015) - [j46]Khondaker Musfakus Salehin, Roberto Rojas-Cessa, Sotirios G. Ziavras
A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines. IEEE Syst. J. 9(4): 1248-1251 (2015) - [j45]Spiridon F. Beldianu, Sotirios G. Ziavras
Performance-Energy Optimizations for Shared Vector Accelerators in Multicores. IEEE Trans. Computers 64(3): 805-817 (2015) - 2014
- [c55]Spiridon F. Beldianu, Sotirios G. Ziavras
ASIC Design of Shared Vector Accelerators for Multicore Processors. SBAC-PAD 2014: 182-189 - 2013
- [j44]Spiridon F. Beldianu, Sotirios G. Ziavras
Multicore-based vector coprocessor sharing for performance and energy gains. ACM Trans. Embed. Comput. Syst. 13(2): 17:1-17:25 (2013) - [c54]Shashank Suresh, Spiridon F. Beldianu, Sotirios G. Ziavras
FPGA and ASIC square root designs for high performance and power efficiency. ASAP 2013: 269-272 - [c53]Nitesh B. Guinde, Roberto Rojas-Cessa, Sotirios G. Ziavras
Packet classification using rule caching. IISA 2013: 1-6 - [c52]Spiridon F. Beldianu, Sotirios G. Ziavras:
Efficient on-chip vector processing for multicore processors. ISSoC 2013: 1-4 - 2012
- [j43]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. IET Comput. Digit. Tech. 6(1): 50-58 (2012) - [j42]Spiridon F. Beldianu, Christopher Dahlberg, Timothy Steele, Sotirios G. Ziavras
Versatile design of shared vector coprocessors for multicores. Microprocess. Microsystems 36(7): 543-554 (2012) - [j41]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 643-654 (2012) - [j40]Imtiaz Sajid, Muhammad Mansoor Ahmed
Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm. J. Signal Process. Syst. 67(2): 157-166 (2012) - [c51]Ioannis Vlahava, Sotirios G. Ziavras
Message from General Chairs. ICTAI 2012 - 2011
- [c50]Spiridon F. Beldianu, Sotirios G. Ziavras
On-chip Vector Coprocessor Sharing for Multicores. PDP 2011: 431-438 - 2010
- [j39]Nitesh B. Guinde, Sotirios G. Ziavras
Efficient hardware support for pattern matching in network intrusion detection. Comput. Secur. 29(7): 756-769 (2010) - [j38]Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras
Scheduling for input-queued packet switches by a re-configurable parallel match evaluator. IEEE Commun. Lett. 14(4): 357-359 (2010) - [j37]Sara Motahari, Sotirios G. Ziavras
Online anonymity protection in computer-mediated communication. IEEE Trans. Inf. Forensics Secur. 5(3): 570-580 (2010) - [c49]Imtiaz Sajid, Sotirios G. Ziavras
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance. DSD 2010: 763-770 - [c48]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. ISVLSI 2010: 310-315 - [c47]Imtiaz Sajid, Sotirios G. Ziavras, Muhammad Mansoor Ahmed:
FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization. VISAPP (2) 2010: 227-232 - [c46]Nitesh B. Guinde, Sotirios G. Ziavras
Novel FPGA-Based Signature Matching for Deep Packet Inspection. WISTP 2010: 261-276
2000 – 2009
- 2009
- [j36]Muhammad Z. Hasan, Sotirios G. Ziavras:
Customized kernel execution on reconfigurable hardware for embedded applications. Microprocess. Microsystems 33(3): 211-220 (2009) - [j35]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Trans. Computers 58(9): 1171-1184 (2009) - [j34]Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 953-963 (2009) - [c45]Sara Motahari, Sotirios G. Ziavras
Social Inference Risk Modeling in Mobile and Social Applications. CSE (3) 2009: 125-132 - [c44]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung:
Exploiting narrow-width values for thermal-aware register file designs. DATE 2009: 1422-1427 - [c43]Sara Motahari, Sotirios G. Ziavras
Identity Inference as a Privacy Risk in Computer-Mediated Communication. HICSS 2009: 1-10 - [c42]Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras
Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches. ICCCN 2009: 1-6 - [c41]Sara Motahari, Sotirios G. Ziavras
Preventing Unwanted Social Inferences with Classification Tree Analysis. ICTAI 2009: 500-507 - [c40]Sara Motahari, Sotirios G. Ziavras, Quentin Jones:
Designing for different levels of social inference risk. SOUPS 2009 - 2008
- [j33]Xin Tang, Constantine N. Manikopoulos, Sotirios G. Ziavras:
Generalized Anomaly Detection Model for Windows-based Malicious Program Behavior . Int. J. Netw. Secur. 7(3): 428-435 (2008) - [j32]Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
Asymmetrically banked value-aware register files for low-energy and high-performance. Microprocess. Microsystems 32(3): 171-182 (2008) - [j31]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1503-1507 (2008) - [j30]Dejiang Jin, Sotirios G. Ziavras
Robust scalability analysis and SPM case studies. J. Supercomput. 43(3): 199-223 (2008) - [c39]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
BTB Access Filtering: A Low Energy and High Performance Design. ISVLSI 2008: 81-86 - 2007
- [j29]Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu:
Reconfiguration support for vector operations. Int. J. High Perform. Syst. Archit. 1(2): 89-97 (2007) - [j28]Sotirios G. Ziavras
Coprocessor design to support MPI primitives in configurable multiprocessors. Integr. 40(3): 235-252 (2007) - [j27]Muhammad Z. Hasan, Sotirios G. Ziavras:
Partially Reconfigurable Vector Processor for Embedded Applications. J. Comput. 2(9): 60-66 (2007) - [c38]Xiaofang Wang, Sotirios G. Ziavras, Jie S. Hu:
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. ERSA 2007: 61-70 - [c37]Muhammad Z. Hasan, Sotirios G. Ziavras
Resource management for dynamically-challenged reconfigurable systems. ETFA 2007: 119-126 - [c36]Kanchan Devarakonda, Sotirios G. Ziavras
Measuring Network Parameters with Hardware Support. ICNS 2007: 2 - [c35]Dejiang Jin, Sotirios G. Ziavras
A Study of Data Exchange Protocols for the Grid Computing Environment. ICNS 2007: 75 - [c34]Xiaofang Wang, Sotirios G. Ziavras
Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. ISQED 2007: 386-391 - [c33]Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
Asymmetrically Banked Value-Aware Register Files. ISVLSI 2007: 363-368 - [c32]Hongyan Yang, Shuai Wang, Sotirios G. Ziavras
Vector Processing Support for FPGA-Oriented High Performance Applications. ISVLSI 2007: 447-448 - [c31]Muhammad Z. Hasan, Sotirios G. Ziavras
Runtime Partial Reconfiguration for Embedded Vector Processors. ITNG 2007: 983-988 - [c30]Hongyan Yang, Sotirios G. Ziavras
FPGA-based Vector Processing for Matrix Operations. ITNG 2007: 989-994 - 2006
- [j26]Xizhen Xu, Sotirios G. Ziavras
A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers. IEICE Trans. Inf. Syst. 89-D(2): 639-646 (2006) - [c29]Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. DSN 2006: 281-290 - [c28]Xiaofang Wang, Sotirios G. Ziavras
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. ICCD 2006: 411-416 - [c27]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ICSAMOS 2006: 14-20 - 2005
- [j25]Dejiang Jin, Sotirios G. Ziavras
Modeling distributed data representation and its effect on parallel data accesses. J. Parallel Distributed Comput. 65(10): 1281-1289 (2005) - [c26]Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras:
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference 2005: 200-214 - [c25]Xizhen Xu, Sotirios G. Ziavras, Tae-Gyu Chang:
An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method. EUC 2005: 458-468 - [c24]Muhammad Z. Hasan, Sotirios G. Ziavras
FPGA-Based Vector Processing for Solving Sparse Sets of Equations. FCCM 2005: 331-332 - [c23]Xiaofang Wang, Sotirios G. Ziavras:
A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors. FPT 2005: 51-58 - [c22]Roberto Rojas-Cessa, Ziqian Dong
Load-balanced CICB packet switch with support for long round-trip times. GLOBECOM 2005: 5 - [c21]Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
Optimizing the Thermal Behavior of Subarrayed Data Caches. ICCD 2005: 625-630 - [c20]Xizhen Xu, Sotirios G. Ziavras
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication. ICCD 2005: 671-676 - [c19]Hongyan Yang, Sotirios G. Ziavras:
FPGA-based vector processor for algebraic equation solvers. SoCC 2005: 115-116 - [c18]Xizhen Xu, Sotirios G. Ziavras:
A hierarchically-controlled SIMD machine for 2D DCT on FPGAs. SoCC 2005: 276-279 - 2004
- [j24]Xiaofang Wang, Sotirios G. Ziavras:
Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines. Concurr. Comput. Pract. Exp. 16(4): 319-343 (2004) - [j23]Dejiang Jin, Sotirios G. Ziavras:
A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters. IEICE Trans. Inf. Syst. 87-D(7): 1774-1781 (2004) - [j22]Satchidanand G. Haridas, Sotirios G. Ziavras
FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. Parallel Algorithms Appl. 19(4): 211-226 (2004) - [j21]Dejiang Jin, Sotirios G. Ziavras
A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters. IEEE Trans. Parallel Distributed Syst. 15(9): 783-794 (2004) - [c17]Xiaofang Wang, Sotirios G. Ziavras:
A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization. IPDPS 2004 - 2003
- [j20]Sotirios G. Ziavras, Qian Wang, Paraskevi Papathanasiou:
Viable Architectures for High-Performance Computing. Comput. J. 46(1): 36-54 (2003) - [j19]Sotirios G. Ziavras
Processor design based on dataflow concurrency. Microprocess. Microsystems 27(4): 199-220 (2003) - [c16]Xizhen Xu, Sotirios G. Ziavras:
Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines. CATA 2003: 472-475 - [c15]Xiaofang Wang, Sotirios G. Ziavras:
Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. FPT 2003: 303-306 - [c14]Dejiang Jin, Sotirios G. Ziavras
Load Balancing on PC Clusters with the Super-Programming Model. ICPP Workshops 2003: 63-70 - [c13]Xiaofang Wang, Sotirios G. Ziavras:
Parallel Direct Solution of Linear Equations on FPGA-Based Machines. IPDPS 2003: 113 - 2002
- [j18]Segreen Ingersoll, Sotirios G. Ziavras
Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs). Microprocess. Microsystems 26(6): 263-280 (2002) - 2001
- [j17]Taras I. Golota, Sotirios G. Ziavras:
A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers. VLSI Design 12(1): 25-52 (2001) - 2000
- [j16]Sotirios G. Ziavras
A new-generation parallel computer and its performance evaluation. Future Gener. Comput. Syst. 17(3): 315-333 (2000) - [c12]Sotirios G. Ziavras:
Versatile Processor Design for Efficiency and High Performance. ISPAN 2000: 266-273
1990 – 1999
- 1999
- [j15]Sotirios G. Ziavras, Sanjay Krishnamurthy:
Evaluating the communications capabilities of the generalized hypercube interconnection network. Concurr. Pract. Exp. 11(6): 281-300 (1999) - [j14]Sotirios G. Ziavras:
Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing. VLSI Design 9(1): 29-54 (1999) - [c11]Qian Wang, Sotirios G. Ziavras:
Network Embedding Techniques for a New Class of Feasible Parallel Architectures. Applied Informatics 1999: 566-568 - [c10]Qian Wang, Sotirios G. Ziavras:
Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. ISPAN 1999: 222-229 - 1998
- [c9]Sotirios G. Ziavras, Qian Wang:
Robust interprocessor connections for very-high performance. Robust Communication Networks: Interconnection and Survivability 1998: 143-167 - 1997
- [j13]Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos:
Parallel generation of adaptive multiresolution structures for image processing. Concurr. Pract. Exp. 9(4): 241-254 (1997) - 1996
- [j12]Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos:
Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture. Concurr. Pract. Exp. 8(5): 387-411 (1996) - [j11]Sotirios G. Ziavras
Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer. Parallel Comput. 22(4): 595-606 (1996) - [c8]Sotirios G. Ziavras:
Performance Analysis for an Important Class of Parallel-Processing Networks. ISPAN 1996: 500-506 - 1995
- [j10]Sotirios G. Ziavras, Michalis A. Sideras:
Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers. Int. J. Pattern Recognit. Artif. Intell. 9(4): 679-698 (1995) - [j9]Sotirios G. Ziavras:
Scalable Multifolded Hypercubes for versatile Parallel Computers. Parallel Process. Lett. 5: 241-250 (1995) - 1994
- [j8]Sotirios G. Ziavras, Devenkumar P. Shah:
High-performance emulation of hierarchical structures on hypercube supercomputers. Concurr. Pract. Exp. 6(2): 85-100 (1994) - [j7]Sotirios G. Ziavras
Adaptive Multiresolution Structures for Image Processing on Parallel Computers. J. Parallel Distributed Comput. 23(3): 475-483 (1994) - [j6]Sotirios G. Ziavras
RH: A Versatile Family of Reduced Hypercube Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 5(11): 1210-1220 (1994) - [c7]Sotirios G. Ziavras:
Generalized reduced hypercube interconnection networks for massively parallel computers. Interconnection Networks and Mapping and Scheduling Parallel Computations 1994: 307-325 - [c6]Sotirios G. Ziavras:
A class of scalable architectures for high-performance, cost-effective parallel computing. SPDP 1994: 162-169 - 1993
- [j5]Sotirios G. Ziavras, Muhammad A. Siddiqui:
Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study. Concurr. Pract. Exp. 5(6): 471-489 (1993) - [j4]Sotirios G. Ziavras
Connected component labelling on the BLITZEN massively parallel processor. Image Vis. Comput. 11(10): 665-668 (1993) - [j3]Sotirios G. Ziavras
Efficient Mapping Algorithms for a Class of Hierarchical Systems. IEEE Trans. Parallel Distributed Syst. 4(11): 1230-1245 (1993) - 1992
- [j2]Sotirios G. Ziavras
On the Problem of Expanding Hypercube-Based Systems. J. Parallel Distributed Comput. 16(1): 41-53 (1992) - [c5]Sotirios G. Ziavras:
Connection Machine Results for Pyramid Embedding Algorithms. CONPAR 1992: 31-36 - [c4]Nagasimha G. Haravu, Sotirios G. Ziavras:
Processor Allocation for a Class of Hypercube-Like Supercomputers. SC 1992: 740-749 - 1990
- [c3]Sotirios G. Ziavras:
Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems. ICPP (1) 1990: 226-233
1980 – 1989
- 1989
- [c2]Sotirios G. Ziavras:
On the mapping problem for multi-level systems. SC 1989: 399-408 - 1988
- [j1]Sotirios G. Ziavras
Improved algorithms for translation of pictures represented by leaf codes. Image Vis. Comput. 6(1): 13-20 (1988) - 1986
- [c1]Nikitas A. Alexandridis, Sotirios G. Ziavras, P. D. Tsanakas:
Architectural Adaptations for Hierarchical Image Processing/Transmission. ICC 1986: 424-428
Coauthor Index
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