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Daniel E. Holcomb
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- affiliation: University of Massachusetts Amherst, MA, USA
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2020 – today
- 2024
- [c46]Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb:
Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes. DATE 2024: 1-6 - [c45]Bharadwaj Madabhushi, Chandra Sekhar Mummidi, Sandip Kundu, Daniel E. Holcomb:
Resurrection Attack: Defeating Xilinx MPU's Memory Protection. HOST 2024: 394-403 - [i17]Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb:
Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes. CoRR abs/2405.13927 (2024) - [i16]Bharadwaj Madabhushi, Chandra Sekhar Mummidi, Sandip Kundu, Daniel E. Holcomb:
Resurrection Attack: Defeating Xilinx MPU's Memory Protection. CoRR abs/2405.13933 (2024) - [i15]Aleksa Deric, Kyle Mitard, Shahin Tajik, Daniel E. Holcomb:
Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques. CoRR abs/2405.14821 (2024) - 2023
- [j20]Xiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb:
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud. ACM Trans. Reconfigurable Technol. Syst. 16(1): 3:1-3:20 (2023) - [j19]Shayan Moini
, Aleksa Deric
Voltage Sensor Implementations for Remote Power Attacks on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 16(1): 11:1-11:21 (2023) - [c44]Shanquan Tian, Shayan Moini, Daniel E. Holcomb, Russell Tessier, Jakub Szefer:
A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs. DATE 2023: 1-6 - [c43]Shayan Moini
Fault Recovery from Multi-Tenant FPGA Voltage Attacks. ACM Great Lakes Symposium on VLSI 2023: 557-562 - [c42]Arjun Suresh
A Secure Design Methodology to Prevent Targeted Trojan Insertion during Fabrication. ISVLSI 2023: 1-6 - [i14]Simon Klix, Nils Albartus, Julian Speith, Paul Staat, Alice Verstege, Annika Wilde, Daniel Lammers, Jörn Langheinrich, Christian Kison, Sebastian Sester, Daniel E. Holcomb, Christof Paar:
Stealing Maggie's Secrets - On the Challenges of IP Theft Through FPGA Reverse Engineering. CoRR abs/2312.06195 (2023) - 2022
- [j18]Aleksa Deric, Daniel E. Holcomb:
Know Time to Die - Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(3): 391-412 (2022) - [j17]Xiaozhe Shao
Accelerating BGP Configuration Verification Through Reducing Cycles in SMT Constraints. IEEE/ACM Trans. Netw. 30(6): 2493-2504 (2022) - [c41]Xiang Li, Russell Tessier
Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs. FCCM 2022: 1-5 - 2021
- [j16]Siddharth Garg, Daniel E. Holcomb
Guest Editors' Introduction: Competing to Secure SoCs. IEEE Des. Test 38(1): 5-6 (2021) - [j15]Shayan Moini
Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 357-370 (2021) - [j14]Chip-Hong Chang, Daniel E. Holcomb, Ulrich Rührmair
The ASHES 2019 special issue at JCEN. J. Cryptogr. Eng. 11(3): 199-200 (2021) - [c40]Shayan Moini, Shanquan Tian, Daniel E. Holcomb, Jakub Szefer, Russell Tessier
Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs. DATE 2021: 1639-1644 - [c39]Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel E. Holcomb, Russell Tessier, Jakub Szefer:
Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs. FCCM 2021: 242-246 - [c38]Julia Burgiel, Daniel E. Holcomb, Ilias Giechaskiel, Shanquan Tian, Jakub Szefer:
Characterization of IOBUF-based Ring Oscillators. FPT 2021: 1-4 - 2020
- [j13]Siva Nishok Dhanuskodi
Techniques to Reduce Switching and Leakage Energy in Unrolled Block Ciphers. IEEE Trans. Computers 69(10): 1414-1423 (2020) - [j12]Siva Nishok Dhanuskodi
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1807-1820 (2020) - [j11]George Provelengios
Power Distribution Attacks in Multitenant FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2685-2698 (2020) - [c37]George Provelengios, Daniel E. Holcomb, Russell Tessier
Power Wasting Circuits for Cloud FPGA Attacks. FPL 2020: 231-235 - [c36]Xiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb:
Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud. FPT 2020: 112-119 - [c35]Shayan Moini
Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs. MWSCAS 2020: 941-944 - [c34]Siva Nishok Dhanuskodi, Xiang Li, Daniel E. Holcomb:
COUNTERFOIL: Verifying Provenance of Integrated Circuits using Intrinsic Package Fingerprints and Inexpensive Cameras. USENIX Security Symposium 2020: 1255-1272 - [i13]Shayan Moini, Shanquan Tian, Jakub Szefer
Remote Power Side-Channel Attacks on CNN Accelerators in FPGAs. CoRR abs/2011.07603 (2020)
2010 – 2019
- 2019
- [j10]Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier:
Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. 11(4): 26:1-26:23 (2019) - [j9]Mohammad A. Usmani
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 364-375 (2019) - [c33]Chip-Hong Chang
ASHES 2019: 3rd Workshop on Attacks and Solutions in Hardware Security. CCS 2019: 2709-2710 - [c32]George Provelengios, Chethan Ramesh, Shivukumar B. Patil, Ken Eguro, Russell Tessier, Daniel E. Holcomb:
Characterization of Long Wire Data Leakage in Deep Submicron FPGAs. FPGA 2019: 292-297 - [c31]George Provelengios, Daniel E. Holcomb, Russell Tessier:
Characterizing Power Distribution Attacks in Multi-User FPGA Environments. FPL 2019: 194-201 - [c30]Siva Nishok Dhanuskodi, Daniel E. Holcomb:
Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility. ISVLSI 2019: 314-319 - [e2]Chip-Hong Chang, Ulrich Rührmair, Daniel E. Holcomb, Patrick Schaumont
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, ASHES@CCS 2019, London, UK, November 15, 2019. ACM 2019, ISBN 978-1-4503-6839-1 [contents] - [i12]Samaneh Ghandali, Daniel E. Holcomb, Christof Paar:
Temperature-Based Hardware Trojan For Ring-Oscillator-Based TRNGs. CoRR abs/1910.00735 (2019) - [i11]Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu:
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques. CoRR abs/1910.00981 (2019) - 2018
- [j8]Shahrzad Keshavarz
Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection. J. Hardw. Syst. Secur. 2(3): 214-224 (2018) - [j7]Xiaolin Xu
Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2431-2442 (2018) - [c29]Chip-Hong Chang
ASHES 2018- Workshop on Attacks and Solutions in Hardware Security. CCS 2018: 2168-2170 - [c28]Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel E. Holcomb, Russell Tessier:
FPGA Side Channel Attacks without Physical Access. FCCM 2018: 45-52 - [c27]Shahrzad Keshavarz, Falk Schellenberg
SAT-based reverse engineering of gate-level schematics using fault injection and probing. HOST 2018: 215-220 - [e1]Chip-Hong Chang, Ulrich Rührmair, Daniel E. Holcomb, Jorge Guajardo:
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, ASHES@CCS 2018, Toronto, ON, Canada, October 19, 2018. ACM 2018, ISBN 978-1-4503-5996-2 [contents] - [i10]Shahrzad Keshavarz, Falk Schellenberg, Bastian Richter, Christof Paar, Daniel E. Holcomb:
SAT-based Reverse Engineering of Gate-Level Schematics using Fault Injection and Probing. CoRR abs/1802.08916 (2018) - [i9]Shahrzad Keshavarz, Daniel E. Holcomb:
Privacy Leakages in Approximate Adders. CoRR abs/1802.08919 (2018) - [i8]Cunxi Yu, Daniel E. Holcomb:
Algorithmic Obfuscation over GF(2m). CoRR abs/1809.06207 (2018) - 2017
- [j6]Cunxi Yu
Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1647-1659 (2017) - [j5]Arunkumar Vijayakumar
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques. IEEE Trans. Inf. Forensics Secur. 12(1): 64-77 (2017) - [c26]Shahrzad Keshavarz
Design automation for obfuscated circuits with multiple viable functions. DATE 2017: 886-889 - [c25]Cunxi Yu
Reverse engineering of irreducible polynomials in GF(2m) arithmetic. DATE 2017: 1558-1563 - [c24]Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier:
Energy Efficient Loop Unrolling for Low-Cost FPGAs. FCCM 2017: 117-120 - [c23]Vinay C. Patil, Arunkumar Vijayakumar, Daniel E. Holcomb, Sandip Kundu:
Improving reliability of weak PUFs via circuit techniques to enhance mismatch. HOST 2017: 146-150 - [c22]Shahrzad Keshavarz, Daniel E. Holcomb:
Threshold-based obfuscated keys with quantifiable security against invasive readout. ICCAD 2017: 57-64 - [c21]Shahrzad Keshavarz, Daniel E. Holcomb:
Privacy leakages in approximate adders. ISCAS 2017: 1-4 - [c20]Siva Nishok Dhanuskodi, Daniel E. Holcomb:
An improved clocking methodology for energy efficient low area AES architectures using register renaming. ISLPED 2017: 1-6 - [i7]Shahrzad Keshavarz, Christof Paar, Daniel E. Holcomb:
Design Automation for Obfuscated Circuits with Multiple Viable Functions. CoRR abs/1703.00475 (2017) - [i6]Shahrzad Keshavarz, Daniel E. Holcomb:
Threshold-based Obfuscated Keys with Quantifiable Security against Invasive Readout. CoRR abs/1708.07150 (2017) - 2016
- [j4]Josiah D. Hester
Persistent Clocks for Batteryless Sensing Devices. ACM Trans. Embed. Comput. Syst. 15(4): 77:1-77:28 (2016) - [c19]Samaneh Ghandali, Georg T. Becker, Daniel E. Holcomb, Christof Paar:
A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks. CHES 2016: 625-647 - [c18]Duo Liu, Cunxi Yu, Xiangyu Zhang, Daniel E. Holcomb:
Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits. DATE 2016: 433-438 - [c17]Xiaolin Xu, Daniel E. Holcomb:
Reliable PUF design using failure patterns from time-controlled power gating. DFT 2016: 135-140 - [c16]Shrikant Vyas, Naveen Kumar Dumpala, Russell Tessier, Daniel E. Holcomb:
Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement. FPL 2016: 1-4 - [c15]Xiaolin Xu, Daniel E. Holcomb:
A Clockless Sequential PUF with Autonomous Majority Voting. ACM Great Lakes Symposium on VLSI 2016: 27-32 - [c14]Siva Nishok Dhanuskodi, Shahrzad Keshavarz, Daniel E. Holcomb:
LLPA: Logic State Based Leakage Power Analysis. ISVLSI 2016: 218-223 - [c13]Xiaolin Xu, Wayne P. Burleson, Daniel E. Holcomb:
Using Statistical Models to Improve the Reliability of Delay-Based PUFs. ISVLSI 2016: 547-552 - [c12]Siva Nishok Dhanuskodi, Daniel E. Holcomb:
Energy Optimization of Unrolled Block Ciphers Using Combinational Checkpointing. RFIDSec 2016: 47-61 - [i5]Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski:
Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic. CoRR abs/1612.04588 (2016) - [i4]Samaneh Ghandali, Georg T. Becker, Daniel E. Holcomb, Christof Paar:
A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks. IACR Cryptol. ePrint Arch. 2016: 600 (2016) - [i3]Siva Nishok Dhanuskodi, Daniel E. Holcomb:
Energy Optimization of Unrolled Block Ciphers using Combinational Checkpointing. IACR Cryptol. ePrint Arch. 2016: 1093 (2016) - 2015
- [j3]Xiaolin Xu, Amir Rahmati
Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 903-914 (2015) - [c11]Amir Rahmati
Probable cause: the deanonymizing effects of approximate DRAM. ISCA 2015: 604-615 - [c10]Xiaolin Xu, Ulrich Rührmair, Daniel E. Holcomb, Wayne P. Burleson:
Security Evaluation and Enhancement of Bistable Ring PUFs. RFIDSec 2015: 3-16 - [i2]Xiaolin Xu, Ulrich Rührmair, Daniel E. Holcomb, Wayne P. Burleson:
Security Evaluation and Enhancement of Bistable Ring PUFs. IACR Cryptol. ePrint Arch. 2015: 443 (2015) - 2014
- [j2]Daniel E. Holcomb, Sanjit A. Seshia:
Compositional Performance Verification of Network-on-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1370-1383 (2014) - [c9]Daniel E. Holcomb, Kevin Fu:
Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM. CHES 2014: 510-526 - [c8]Ulrich Rührmair, Daniel E. Holcomb:
PUFs at a glance. DATE 2014: 1-6 - [i1]Daniel E. Holcomb, Kevin Fu:
Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM. IACR Cryptol. ePrint Arch. 2014: 749 (2014) - 2013
- [b1]Daniel E. Holcomb:
Formal Verification and Synthesis for Quality-of-Service in On-Chip Networks. University of California, Berkeley, USA, 2013 - 2012
- [c7]Daniel E. Holcomb, Alexander Gotmanov, Michael Kishinevsky, Sanjit A. Seshia:
Compositional performance verification of NoC designs. MEMOCODE 2012: 1-10 - [c6]Daniel E. Holcomb, Amir Rahmati
DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification. RFIDSec 2012: 165-179 - [c5]Amir Rahmati, Mastooreh Salajegheh, Daniel E. Holcomb, Jacob Sorber, Wayne P. Burleson, Kevin Fu:
TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks. USENIX Security Symposium 2012: 221-236 - 2011
- [c4]Daniel E. Holcomb, Bryan A. Brady, Sanjit A. Seshia:
Abstraction-based performance verification of NoCs. DAC 2011: 492-497 - [c3]Bryan A. Brady, Daniel E. Holcomb, Sanjit A. Seshia:
Counterexample-guided SMT-driven optimal buffer sizing. DATE 2011: 329-334 - 2010
- [c2]Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne P. Burleson:
Low-power sub-threshold design of secure physical unclonable functions. ISLPED 2010: 43-48
2000 – 2009
- 2009
- [j1]Daniel E. Holcomb, Wayne P. Burleson, Kevin Fu:
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers. IEEE Trans. Computers 58(9): 1198-1210 (2009) - [c1]Daniel E. Holcomb, Wenchao Li, Sanjit A. Seshia:
Design as you see FIT: System-level soft error analysis of sequential circuits. DATE 2009: 785-790
Coauthor Index
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