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Junwhan Ahn
Person information
- affiliation: Google
- affiliation (former): Seoul National University, Department of Electrical and Computer Engineering
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2020 – today
- 2023
- [i3]Rohan Anil, Andrew M. Dai, Orhan Firat, Melvin Johnson, Dmitry Lepikhin, Alexandre Passos, Siamak Shakeri, Emanuel Taropa, Paige Bailey, Zhifeng Chen, Eric Chu, Jonathan H. Clark, Laurent El Shafey, Yanping Huang, Kathy Meier-Hellstern, Gaurav Mishra, Erica Moreira, Mark Omernick, Kevin Robinson, Sebastian Ruder, Yi Tay, Kefan Xiao, Yuanzhong Xu, Yujing Zhang, Gustavo Hernández Ábrego, Junwhan Ahn, Jacob Austin, Paul Barham, Jan A. Botha, James Bradbury, Siddhartha Brahma, Kevin Brooks, Michele Catasta, Yong Cheng, Colin Cherry, Christopher A. Choquette-Choo, Aakanksha Chowdhery, Clément Crepy, Shachi Dave, Mostafa Dehghani, Sunipa Dev, Jacob Devlin, Mark Díaz, Nan Du, Ethan Dyer, Vladimir Feinberg, Fangxiaoyu Feng, Vlad Fienber, Markus Freitag, Xavier Garcia, Sebastian Gehrmann, Lucas Gonzalez, et al.:
PaLM 2 Technical Report. CoRR abs/2305.10403 (2023) - [i2]Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. CoRR abs/2306.15577 (2023) - 2020
- [c22]Evan Zheran Liu, Milad Hashemi, Kevin Swersky, Parthasarathy Ranganathan, Junwhan Ahn:
An Imitation Learning Approach for Cache Replacement. ICML 2020: 6237-6247 - [i1]Evan Zheran Liu, Milad Hashemi, Kevin Swersky, Parthasarathy Ranganathan, Junwhan Ahn:
An Imitation Learning Approach for Cache Replacement. CoRR abs/2006.16239 (2020)
2010 – 2019
- 2019
- [c21]H. Andrés Lagar-Cavilla, Junwhan Ahn, Suleiman Souhlal, Neha Agarwal, Radoslaw Burny, Shakeel Butt, Jichuan Chang, Ashwin Chaugule, Nan Deng, Junaid Shahid, Greg Thelen, Kamil Adam Yurtsever, Yu Zhao, Parthasarathy Ranganathan:
Software-Defined Far Memory in Warehouse-Scale Computers. ASPLOS 2019: 317-330 - 2018
- [j10]Dongyoung Kim, Junwhan Ahn
, Sungjoo Yoo
ZeNA: Zero-Aware Neural Network Accelerator. IEEE Des. Test 35(1): 39-46 (2018) - [j9]Namhyung Kim, Junwhan Ahn
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. ACM Trans. Archit. Code Optim. 15(1): 10:1-10:23 (2018) - [j8]Mungyu Son, Junwhan Ahn, Sungjoo Yoo
Nonvolatile Write Buffer-Based Journaling Bypass for Storage Write Reduction in Mobile Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1747-1759 (2018) - 2017
- [c20]Eunhyeok Park, Junwhan Ahn, Sungjoo Yoo:
Weighted-Entropy-Based Quantization for Deep Neural Networks. CVPR 2017: 7197-7205 - [c19]Mungyu Son, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo:
Making DRAM Stronger Against Row Hammering. DAC 2017: 55:1-55:6 - [c18]Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo:
A novel zero weight/activation-aware hardware architecture of convolutional neural network. DATE 2017: 1462-1467 - 2016
- [j7]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy. ACM Trans. Archit. Code Optim. 13(4): 34:1-34:24 (2016) - [j6]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture. IEEE Trans. Computers 65(3): 940-951 (2016) - [j5]Sungkwang Lee, Taemin Lee, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo, Youjip Won, Sunggu Lee:
Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study. ACM Trans. Design Autom. Electr. Syst. 21(3): 47:1-47:25 (2016) - [j4]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 453-464 (2016) - [c17]Hyunsun Park, Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo:
Zero and data reuse-aware fast convolution for deep neural networks on GPU. CODES+ISSS 2016: 33:1-33:10 - 2015
- [c16]Jinho Lee
THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures. ASP-DAC 2015: 773-778 - [c15]Mungyu Son, Junwhan Ahn, Sungjoo Yoo:
A tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones. CODES+ISSS 2015: 21-29 - [c14]Eunhyeok Park, Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Sunggu Lee:
Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing. DATE 2015: 1341-1346 - [c13]Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
A scalable processing-in-memory accelerator for parallel graph processing. ISCA 2015: 105-117 - [c12]Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. ISCA 2015: 336-348 - [c11]Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi:
Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. VLSI-SoC 2015: 183-188 - [c10]Hyunsun Park, Junwhan Ahn, Eunhyeok Park, Sungjoo Yoo:
Locality-aware vertex scheduling for GPU-based graph computation. VLSI-SoC 2015: 195-200 - 2014
- [j3]Junwhan Ahn, Kiyoung Choi:
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1197-1201 (2014) - [c9]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes. DAC 2014: 139:1-139:6 - [c8]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture. HPCA 2014: 25-36 - 2013
- [j2]Kyuseung Han, Junwhan Ahn, Kiyoung Choi:
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. ACM Trans. Archit. Code Optim. 10(2): 8:1-8:25 (2013) - [j1]Junwhan Ahn, Kiyoung Choi:
Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 34-46 (2013) - [c7]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. ASP-DAC 2013: 285-290 - [c6]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Write intensity prediction for energy-efficient non-volatile caches. ISLPED 2013: 223-228 - 2012
- [c5]Junwhan Ahn, Kiyoung Choi:
Lower-bits cache for low power STT-RAM caches. ISCAS 2012: 480-483 - [c4]Dongwoo Lee
A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem. ISOCC 2012: 159-162 - [c3]Di Wu, Junwhan Ahn, Imyong Lee, Kiyoung Choi:
Resource-shared custom instruction generation under performance/area constraints. ISSoC 2012: 1-6 - 2011
- [c2]Junwhan Ahn, Imyong Lee, Kiyoung Choi:
A polynomial-time custom instruction identification algorithm based on dynamic programming. ASP-DAC 2011: 573-578 - [c1]Junwhan Ahn, Kiyoung Choi:
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. CODES+ISSS 2011: 345-354
Coauthor Index
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