Improved Image Classification using Lightweight Deep Neural Network Enhancements.

Spyros Tragoudas

Vasileios Pentsos Spyros Tragoudas Kiriti Nagesh Gowda Mike Schmit Improved Image Classification using Lightweight Deep Neural Network Enhancements. 2026 February 22:1-22:26 17 ACM Trans. Intell. Syst. Technol. 1 https://doi.org/10.1145/3779421 db/journals/tist/tist17.html#PentsosTGS26 streams/journals/tist

Danushka Senarathna Spyros Tragoudas Jason Wibbenmeyer Nasser Khdeer Time Series Analysis Neural Networks for Detecting False Data Injection Attacks of Different Rates on Power Grid State Estimation. 36:1-36:29 2025 August 28 ACM Trans. Priv. Secur. 3 https://doi.org/10.1145/3723164 db/journals/tissec/tissec28.html#SenarathnaTWK25 streams/journals/tissec

Vasileios Pentsos Spyros Tragoudas Jason Wibbenmeyer Nasser Khdeer A Hybrid LSTM-Transformer Model for Power Load Forecasting. 2624-2634 2025 May 16 IEEE Trans. Smart Grid 3 https://doi.org/10.1109/TSG.2025.3535407 db/journals/tsg/tsg16.html#PentsosTWK25 streams/journals/tsg

Vasileios Pentsos Spyros Tragoudas Kiriti Nagesh Gowda Mike Schmit Energy-Aware DNN Task Scheduling with Dynamic Batching and Frequency Adjustment. 1-8 2025 ISQED https://doi.org/10.1109/ISQED65160.2025.11014389 conf/isqed/2025 db/conf/isqed/isqed2025.html#PentsosTGS25 Aikaterini Maria Panteleaki Varatheepan Paramanayakam Vasileios Pentsos Andreas Karatzas Spyros Tragoudas Iraklis Anagnostopoulos A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data Centers. 1-6 2025 ISVLSI https://doi.org/10.1109/ISVLSI65124.2025.11130313 conf/isvlsi/2025 db/conf/isvlsi/isvlsi2025.html#PanteleakiPPKTA25 streams/conf/isvlsi Iresh M. Jayawardana Krishna Dahal Spyros Tragoudas Khader S. Abdel-Hafez Danushka Senarathna Deep Learning-based IC Monitoring. 522-525 2025 ITC https://doi.org/10.1109/ITC58126.2025.00080 conf/itc/2025 db/conf/itc/itc2025.html#JayawardanaDTAS25 streams/conf/itc

Aikaterini Maria Panteleaki Varatheepan Paramanayakam Vasileios Pentsos Andreas Karatzas Spyros Tragoudas Iraklis Anagnostopoulos A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data Centers. 2025 June abs/2506.01712 CoRR https://doi.org/10.48550/arXiv.2506.01712 db/journals/corr/corr2506.html#abs-2506-01712 streams/journals/corr

Chinthana Wimalasuriya Spyros Tragoudas A Statistical Method for Attack-Agnostic Adversarial Attack Detection with Compressive Sensing Comparison. 2025 October abs/2510.02707 CoRR https://doi.org/10.48550/arXiv.2510.02707 db/journals/corr/corr2510.html#abs-2510-02707 streams/journals/corr

Bijay Raj Paudel Spyros Tragoudas Memristive Crossbar Array-Based Adversarial Defense Using Compression. 864-877 2024 July - September 12 IEEE Trans. Emerg. Top. Comput. 3 https://doi.org/10.1109/TETC.2023.3319659 db/journals/tetc/tetc12.html#PaudelT24 streams/journals/tetc

Danuka Malinda Danushka Senarathna Spyros Tragoudas Enhanced Distribution Matching for Multiclass Quantification. 1238-1242 2024 ICMLA https://doi.org/10.1109/ICMLA61862.2024.00192 conf/icmla/2024 db/conf/icmla/icmla2024.html#MalindaST24 streams/conf/icmla Vasileios Pentsos Spyros Tragoudas A statistical approach to improve CNN classification accuracy. 1-5 2023 HPSR https://doi.org/10.1109/HPSR57248.2023.10148033 conf/hpsr/2023 db/conf/hpsr/hpsr2023.html#PentsosT23 Danushka Senarathna Spyros Tragoudas Kiriti Nagesh Gowda Mike Schmit Detection and Quantization of Data Drift in Image Classification Neural Networks. 38-42 2023 HPSR https://doi.org/10.1109/HPSR57248.2023.10147972 conf/hpsr/2023 db/conf/hpsr/hpsr2023.html#SenarathnaTGS23 Danushka Senarathna Rezoan Ferdous Spyros Tragoudas An Enhanced YOLO Failure Detection Method. 958-965 2023 ICMLA https://doi.org/10.1109/ICMLA58977.2023.00142 conf/icmla/2023 db/conf/icmla/icmla2023.html#SenarathnaFT23 Bijay Raj Paudel Spyros Tragoudas Adversarial Defense using Memristors and Input Preprocessing <sup>*</sup>. 1-5 2023 ISCAS https://doi.org/10.1109/ISCAS46773.2023.10181384 conf/iscas/2023 db/conf/iscas/iscas2023.html#PaudelT23 Bijay Raj Paudel Haibo Wang 0005 Spyros Tragoudas Omkar Rijal High Precision Winner-Take-All Circuit for Neural Networks. 1-6 2023 SOCC https://doi.org/10.1109/SOCC58585.2023.10256761 conf/socc/2023 db/conf/socc/socc2023.html#PaudelWTR23 Danushka Senarathna Spyros Tragoudas Deep Neural Network-Based Accelerators for Repetitive Boolean Logic Evaluation. 1-6 2023 SOCC https://doi.org/10.1109/SOCC58585.2023.10256911 conf/socc/2023 db/conf/socc/socc2023.html#SenarathnaT23

Xiaoqian Chen Lalit Gupta Spyros Tragoudas Improving the Forecasting and Classification of Extreme Events in Imbalanced Time Series Through Block Resampling in the Joint Predictor-Forecast Space. 121048-121079 2022 10 IEEE Access https://doi.org/10.1109/ACCESS.2022.3219832 db/journals/access/access10.html#ChenGT22

Krishna Prasad Gnawali Spyros Tragoudas High-Speed Memristive Ternary Content Addressable Memory. 1349-1360 2022 10 IEEE Trans. Emerg. Top. Comput. 3 https://doi.org/10.1109/TETC.2021.3085252 db/journals/tetc/tetc10.html#GnawaliT22

Bijay Raj Paudel Spyros Tragoudas Compressed Learning in MCA Architectures to Tolerate Malicious Noise. 1-8 2022 IOLTS https://doi.org/10.1109/IOLTS56730.2022.9897622 conf/iolts/2022 db/conf/iolts/iolts2022.html#PaudelT22 Bijay Raj Paudel Vasileios Pentsos Spyros Tragoudas On the Resiliency of an Analog Memristive Architecture against Adversarial Attacks. 1-7 2022 ISQED https://doi.org/10.1109/ISQED54688.2022.9806277 conf/isqed/2022 db/conf/isqed/isqed2022.html#PaudelPT22 Danushka Senarathna Spyros Tragoudas Computation of Soft Error Rates Considering Test Pattern Sequences. 1-6 2022 ISQED https://doi.org/10.1109/ISQED54688.2022.9806212 conf/isqed/2022 db/conf/isqed/isqed2022.html#SenarathnaT22 Bijay Raj Paudel Spyros Tragoudas The Impact of On-chip Training to Adversarial Attacks in Memristive Crossbar Arrays. 519-523 2022 ITC https://doi.org/10.1109/ITC50671.2022.00064 conf/itc/2022 db/conf/itc/itc2022.html#PaudelT22 Puneet Ramesh Savanur Spyros Tragoudas A Fault Model to Detect Design Errors in Combinational Circuits. 1-4 2021 DFT https://doi.org/10.1109/DFT52944.2021.9568351 conf/dft/2021 db/conf/dft/dft2021.html#SavanurT21 Bijay Raj Paudel Danushka Senarathna Haibo Wang 0005 Spyros Tragoudas Yao Hu Shengbing Jiang Predicting YOLO Misdetection by Learning Grid Cell Consensus. 643-648 2021 ICMLA https://doi.org/10.1109/ICMLA52953.2021.00107 conf/icmla/2021 db/conf/icmla/icmla2021.html#PaudelSWTHJ21 Bijay Raj Paudel Aashish Itani Spyros Tragoudas Resiliency of SNN on Black-Box Adversarial Attacks. 799-806 2021 ICMLA https://doi.org/10.1109/ICMLA52953.2021.00132 conf/icmla/2021 db/conf/icmla/icmla2021.html#PaudelIT21 Vasileios Pentsos Bijay Raj Paudel Spyros Tragoudas Kiriti Nagesh Gowda Mike Schmit Improved CNN classification accuracy with the addition of shallow cascading CNNs. 988-991 2021 ICMLA https://doi.org/10.1109/ICMLA52953.2021.00162 conf/icmla/2021 db/conf/icmla/icmla2021.html#PentsosPTGS21

Adam Watkins Spyros Tragoudas Radiation Hardened Latch Designs for Double and Triple Node Upsets. 616-626 2020 8 IEEE Trans. Emerg. Top. Comput. 3 https://doi.org/10.1109/TETC.2017.2776285 db/journals/tetc/tetc8.html#WatkinsT20

Pavan Kumar Javvaji Spyros Tragoudas Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays. 163-173 2020 28 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2019.2941426 db/journals/tvlsi/tvlsi28.html#JavvajiT20

Basim Shanyour Spyros Tragoudas Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors. 1-3 2020 IOLTS https://doi.org/10.1109/IOLTS50870.2020.9159713 conf/iolts/2020 db/conf/iolts/iolts2020.html#ShanyourT20

Pavan Kumar Javvaji Spyros Tragoudas On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations. 1196-1205 2019 27 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2019.2893844 db/journals/tvlsi/tvlsi27.html#JavvajiT19

Krishna Prasad Gnawali Seyed Nima Mozaffari Spyros Tragoudas Low Power Artificial Neural Network Architecture. 2019 abs/1904.02183 CoRR http://arxiv.org/abs/1904.02183 db/journals/corr/corr1904.html#abs-1904-02183

Seyed Nima Mozaffari Spyros Tragoudas Themistoklis Haniotakis A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions. 946-959 2018 65-I IEEE Trans. Circuits Syst. I Regul. Pap. 3 https://doi.org/10.1109/TCSI.2017.2768563 db/journals/tcas/tcasI65.html#MozaffariTH18

Pavan Kumar Javvaji Spyros Tragoudas A Method to Model Statistical Path Delays for Accurate Defect Coverage. 1-6 2018 DFT https://doi.org/10.1109/DFT.2018.8602962 https://doi.ieeecomputersociety.org/10.1109/DFT.2018.8602962 conf/dft/2018 db/conf/dft/dft2018.html#JavvajiT18 Puneet Ramesh Savanur Spyros Tragoudas Threshold Voltage Extraction Using Static NBTI Aging. 1-6 2018 DFT https://doi.org/10.1109/DFT.2018.8602814 https://doi.ieeecomputersociety.org/10.1109/DFT.2018.8602814 conf/dft/2018 db/conf/dft/dft2018.html#SavanurT18 Pavan Kumar Javvaji Spyros Tragoudas Ganesh Kondapuram Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection. 1-5 2018 ISCAS https://doi.org/10.1109/ISCAS.2018.8351284 conf/iscas/2018 db/conf/iscas/iscas2018.html#JavvajiTK18 Pavan Kumar Javvaji Basim Shanyour Spyros Tragoudas Test set identification for improved delay defect coverage in the presence of statistical delays. 14-19 2018 ISQED https://doi.org/10.1109/ISQED.2018.8357258 conf/isqed/2018 db/conf/isqed/isqed2018.html#JavvajiST18 Basim Shanyour Spyros Tragoudas Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors. 1-10 2018 ITC https://doi.org/10.1109/TEST.2018.8624715 conf/itc/2018 db/conf/itc/itc2018.html#ShanyourT18 Seyed Nima Mozaffari Krishna Prasad Gnawali Spyros Tragoudas An Aging Resilient Neural Network Architecture. 25-30 2018 NANOARCH https://doi.org/10.1145/3232195.3232208 https://ieeexplore.ieee.org/document/8604468 https://www.wikidata.org/entity/Q130978247 conf/nanoarch/2018 db/conf/nanoarch/nanoarch2018.html#MozaffariGT18

Stefan Leitner Haibo Wang 0005 Spyros Tragoudas Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges. 1750035:1-1750035:21 2017 26 J. Circuits Syst. Comput. 2 https://doi.org/10.1142/S0218126617500359 db/journals/jcsc/jcsc26.html#LeitnerWT17

Ahish Mysore Somashekar Spyros Tragoudas Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements. 325-335 2017 36 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/TCAD.2016.2571849 db/journals/tcad/tcad36.html#SomashekarT17

Seyed Nima Mozaffari Spyros Tragoudas Themistoklis Haniotakis More Efficient Testing of Metal-Oxide Memristor-Based Memory. 1018-1029 2017 36 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/TCAD.2016.2608863 db/journals/tcad/tcad36.html#MozaffariTH17

Chandra Babu Dara Themistoklis Haniotakis Spyros Tragoudas Delay Analysis for Current Mode Threshold Logic Gate Designs. 1063-1071 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/TVLSI.2016.2608953 db/journals/tvlsi/tvlsi25.html#DaraHT17

Seyed Nima Mozaffari Spyros Tragoudas Themistoklis Haniotakis A new method to identify threshold logic functions. 934-937 2017 DATE https://doi.org/10.23919/DATE.2017.7927124 http://dl.acm.org/citation.cfm?id=3130602 conf/date/2017 db/conf/date/date2017.html#MozaffariTH17 Ahish Mysore Somashekar Spyros Tragoudas Efficient Critical Path Selection Under a Probabilistic Delay Model. 185-190 2017 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3060403.3060468 conf/glvlsi/2017 db/conf/glvlsi/glvlsi2017.html#SomashekarT17 Theodoros Toulas Spyros Tragoudas Diagnosis with transition faults on embedded segments. 25-27 2017 IOLTS https://doi.org/10.1109/IOLTS.2017.8046173 conf/iolts/2017 db/conf/iolts/iolts2017.html#ToulasT17 Pavan Kumar Javvaji Spyros Tragoudas Efficient computation of the sensitization probability of a critical path considering process variations and path correlation. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050439 conf/iscas/2017 db/conf/iscas/iscas2017.html#JavvajiT17 Seyed Nima Mozaffari Spyros Tragoudas Themistoklis Haniotakis Reducing power, area, and delay of threshold logic gates considering non-integer weights. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050380 conf/iscas/2017 db/conf/iscas/iscas2017.html#MozaffariTH17 Adam Watkins Spyros Tragoudas METS: A multiple event transient simulator. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050442 conf/iscas/2017 db/conf/iscas/iscas2017.html#WatkinsT17 Phaninder Alladi Spyros Tragoudas Aging-aware critical paths for process related validation in the presence of NBTI. 445-448 2017 ISQED https://doi.org/10.1109/ISQED.2017.7918356 conf/isqed/2017 db/conf/isqed/isqed2017.html#AlladiT17

Ashok Kumar Palaniswamy Spyros Tragoudas Themistoklis Haniotakis ATPG for Delay Defects in Current Mode Threshold Logic Circuits. 1903-1913 2016 35 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2016.2533863 db/journals/tcad/tcad35.html#PalaniswamyTH16

Ahish Mysore Somashekar Spyros Tragoudas Rathish Jayabharathi Sreenivas Gangadhar Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection. 17:1-17:21 2016 22 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/2940327 db/journals/todaes/todaes22.html#SomashekarTJG16

Adam Watkins Spyros Tragoudas A Highly Robust Double Node Upset Tolerant latch. 15-20 2016 DFT https://doi.org/10.1109/DFT.2016.7684062 https://doi.ieeecomputersociety.org/10.1109/DFT.2016.7684062 conf/dft/2016 db/conf/dft/dft2016.html#WatkinsT16 Wisam Aljubouri Spyros Tragoudas Themistoklis Haniotakis Identification of delay defects on embedded paths using one current sensor. 1-4 2016 DTIS https://doi.org/10.1109/DTIS.2016.7483809 conf/dtis/2016 db/conf/dtis/dtis2016.html#AljubouriTH16 Phaninder Alladi Spyros Tragoudas Efficient selection of critical paths for delay defects in the presence of process variations. 1-6 2016 DTIS https://doi.org/10.1109/DTIS.2016.7483873 conf/dtis/2016 db/conf/dtis/dtis2016.html#AlladiT16 Adam Watkins Spyros Tragoudas An Enhanced Analytical Electrical Masking Model for Multiple Event Transients. 369-372 2016 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/2902961.2903007 conf/glvlsi/2016 db/conf/glvlsi/glvlsi2016.html#WatkinsT16 Stefan Leitner Haibo Wang 0005 Spyros Tragoudas Compressive image sensor technique with sparse measurement matrix. 223-228 2016 SoCC https://doi.org/10.1109/SOCC.2016.7905472 conf/socc/2016 db/conf/socc/socc2016.html#LeitnerWT16 Puneet Ramesh Savanur Phaninder Alladi Spyros Tragoudas A BIST approach for counterfeit circuit detection based on NBTI degradation. 123-126 2015 DFTS https://doi.org/10.1109/DFT.2015.7315148 https://doi.ieeecomputersociety.org/10.1109/DFT.2015.7315148 conf/dft/2015 db/conf/dft/dft2015.html#SavanurAT15 Ahish Mysore Somashekar Spyros Tragoudas Rathish Jayabharathi Non-enumerative correlation-aware path selection. 629-634 2015 ICCD https://doi.org/10.1109/ICCD.2015.7357174 https://doi.ieeecomputersociety.org/10.1109/ICCD.2015.7357174 conf/iccd/2015 db/conf/iccd/iccd2015.html#SomashekarTJ15 Joseph Lenox Spyros Tragoudas Towards Trojan circuit detection with maximum state transition exploration. 50-52 2015 IOLTS https://doi.org/10.1109/IOLTS.2015.7229831 conf/iolts/2015 db/conf/iolts/iolts2015.html#LenoxT15 Luke Pierce Spyros Tragoudas Unreachable code identification for improved line coverage. 345-351 2015 ISQED https://doi.org/10.1109/ISQED.2015.7085450 conf/isqed/2015 db/conf/isqed/isqed2015.html#PierceT15 Seyed Nima Mozaffari Spyros Tragoudas Themistoklis Haniotakis Fast march tests for defects in resistive memory. 88-93 2015 NANOARCH https://doi.org/10.1109/NANOARCH.2015.7180592 https://doi.ieeecomputersociety.org/10.1109/NANOARCH.2015.7180592 conf/nanoarch/2015 db/conf/nanoarch/nanoarch2015.html#MozaffariTH15

Luke Pierce Spyros Tragoudas Nanopipelined threshold network synthesis. 17:1-17:17 2014 10 ACM J. Emerg. Technol. Comput. Syst. 2 https://doi.org/10.1145/2564924 db/journals/jetc/jetc10.html#PierceT14

Ashok Kumar Palaniswamy Spyros Tragoudas Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms. 21:1-21:32 2014 10 ACM J. Emerg. Technol. Comput. Syst. 3 https://doi.org/10.1145/2597175 https://www.wikidata.org/entity/Q130867523 db/journals/jetc/jetc10.html#PalaniswamyT14

Pragyan (Sheela) Mohanty Spyros Tragoudas Scalable Offline Searches in DNA Sequences. 18:1-18:25 2014 11 ACM J. Emerg. Technol. Comput. Syst. 2 https://doi.org/10.1145/2660774 db/journals/jetc/jetc11.html#MohantyT14

Kedar Karmarkar Spyros Tragoudas On-Chip Codeword Generation to Cope With Crosstalk. 237-250 2014 33 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/TCAD.2013.2284017 db/journals/tcad/tcad33.html#KarmarkarT14

Joseph Lenox Spyros Tragoudas Adapting an Implicit Path Delay Grading Method for Parallel Architectures. 1965-1976 2014 33 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2014.2356438 db/journals/tcad/tcad33.html#LenoxT14

Kedar Karmarkar Spyros Tragoudas Error Correction Encoding for Tightly Coupled On-Chip Buses. 2571-2584 2014 22 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2014.2300095 db/journals/tvlsi/tvlsi22.html#KarmarkarT14

Wisam Aljubouri Ahish Mysore Somashekar Themistoklis Haniotakis Spyros Tragoudas Diagnosis of segment delay defects with current sensing. 122-127 2014 DFT https://doi.org/10.1109/DFT.2014.6962101 https://doi.ieeecomputersociety.org/10.1109/DFT.2014.6962101 conf/dft/2014 db/conf/dft/dft2014.html#AljubouriSHT14 Ashok Kumar Palaniswamy Spyros Tragoudas Themistoklis Haniotakis ATPG for transition faults of pipelined threshold logic circuits. 1-5 2014 DTIS https://doi.org/10.1109/DTIS.2014.6850662 conf/dtis/2014 db/conf/dtis/dtis2014.html#PalaniswamyTH14 Adam Watkins Venkata Naresh Mudhireddy Haibo Wang 0005 Spyros Tragoudas Adaptive compressive sensing for low power wireless sensors. 99-104 2014 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/2591513.2591537 conf/glvlsi/2014 db/conf/glvlsi/glvlsi2014.html#WatkinsMWT14 Joseph Lenox Spyros Tragoudas A novel parallel adaptation of an implicit path delay grading method. 217-222 2014 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/2591513.2591539 conf/glvlsi/2014 db/conf/glvlsi/glvlsi2014.html#LenoxT14 Phaninder Alladi Spyros Tragoudas Aging-aware critical paths in deep submicron. 184-185 2014 IOLTS https://doi.org/10.1109/IOLTS.2014.6873691 conf/iolts/2014 db/conf/iolts/iolts2014.html#AlladiT14

Sreenivas Gangadhar Spyros Tragoudas A Probabilistic Approach to Diagnose SETs in Sequential Circuits. 317-330 2013 29 J. Electron. Test. 3 https://doi.org/10.1007/s10836-013-5361-4 db/journals/et/et29.html#GangadharT13

Luke Pierce Spyros Tragoudas Enhanced Secure Architecture for Joint Action Test Group Systems. 1342-1345 2013 21 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2012.2208209 db/journals/tvlsi/tvlsi21.html#PierceT13

Chandra Babu Dara Themistoklis Haniotakis Spyros Tragoudas Low power and high speed current-mode memristor-based TLGs. 89-94 2013 DFTS https://doi.org/10.1109/DFT.2013.6653588 https://doi.ieeecomputersociety.org/10.1109/DFT.2013.6653588 conf/dft/2013 db/conf/dft/dft2013.html#DaraHT13 Kedar Karmarkar Spyros Tragoudas Error detection encoding for multi-threshold capture mechanism. 92-97 2013 IOLTS https://doi.org/10.1109/IOLTS.2013.6604057 conf/iolts/2013 db/conf/iolts/iolts2013.html#KarmarkarT13 Ahish Mysore Somashekar Spyros Tragoudas Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements. 481-486 2013 ISQED https://doi.org/10.1109/ISQED.2013.6523655 conf/isqed/2013 db/conf/isqed/isqed2013.html#SomashekarT13 Dheepakkumaran Jayaraman Spyros Tragoudas Performance validation through implicit removal of infeasible paths of the behavioral description. 552-557 2013 ISQED https://doi.org/10.1109/ISQED.2013.6523665 conf/isqed/2013 db/conf/isqed/isqed2013.html#JayaramanT13 Dheepakkumaran Jayaraman Spyros Tragoudas A method to determine the sensitization probability of a non-robustly testable path. 676-681 2013 ISQED https://doi.org/10.1109/ISQED.2013.6523683 conf/isqed/2013 db/conf/isqed/isqed2013.html#JayaramanT13a

Khadija Jirari Stewart Themistoklis Haniotakis Spyros Tragoudas Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission. 328-338 2012 10 Ad Hoc Networks 3 https://doi.org/10.1016/j.adhoc.2011.06.017 db/journals/adhoc/adhoc10.html#StewartHT12

Ashok Kumar Palaniswamy Spyros Tragoudas An efficient heuristic to identify threshold logic functions. 19:1-19:17 2012 8 ACM J. Emerg. Technol. Comput. Syst. 3 https://doi.org/10.1145/2287696.2287702 https://www.wikidata.org/entity/Q130887595 db/journals/jetc/jetc8.html#PalaniswamyT12

Michael N. Skoufis Spyros Tragoudas An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic. 187-198 2012 61 IEEE Trans. Computers 2 https://doi.org/10.1109/TC.2010.259 http://doi.ieeecomputersociety.org/10.1109/TC.2010.259 db/journals/tc/tc61.html#SkoufisT12

Sreenivas Gangadhar Spyros Tragoudas Accurate calculation of SET propagation probability for hardening. 104-108 2012 DFT https://doi.org/10.1109/DFT.2012.6378208 https://doi.ieeecomputersociety.org/10.1109/DFT.2012.6378208 conf/dft/2012 db/conf/dft/dft2012.html#GangadharT12 Adam Watkins Spyros Tragoudas Transient pulse propagation using the Weibull distribution function. 109-114 2012 DFT https://doi.org/10.1109/DFT.2012.6378209 https://doi.ieeecomputersociety.org/10.1109/DFT.2012.6378209 conf/dft/2012 db/conf/dft/dft2012.html#WatkinsT12 Ashok Kumar Palaniswamy Spyros Tragoudas A scalable threshold logic synthesis method using ZBDDs. 307-310 2012 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/2206781.2206856 https://www.wikidata.org/entity/Q130878642 conf/glvlsi/2012 db/conf/glvlsi/glvlsi2012.html#PalaniswamyT12 Ahish Mysore Somashekar Spyros Tragoudas Sreenivas Gangadhar Rathish Jayabharathi Non-enumerative generation of statistical path delays for ATPG. 514-515 2012 ICCD https://doi.org/10.1109/ICCD.2012.6378700 https://doi.ieeecomputersociety.org/10.1109/ICCD.2012.6378700 conf/iccd/2012 db/conf/iccd/iccd2012.html#SomashekarTGJ12 Chandra Babu Dara Themistoklis Haniotakis Spyros Tragoudas Delay Analysis for an N-Input Current Mode Threshold Logic Gate. 344-349 2012 ISVLSI https://doi.org/10.1109/ISVLSI.2012.34 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2012.34 conf/isvlsi/2012 db/conf/isvlsi/isvlsi2012.html#DaraHT12

Rajsekhar Adapa Spyros Tragoudas Maria K. Michael Improved diagnosis using enhanced fault dominance. 217-228 2011 44 Integr. 3 https://doi.org/10.1016/j.vlsi.2011.01.002 db/journals/integration/integration44.html#AdapaTM11

Pragyan P. Mohanty Spyros Tragoudas A Scalable Method for Identifying DNA Substrings Using Functions. 178-183 2011 BICoB conf/bicob/2011 db/conf/bicob/bicob2011.html#MohantyT11 Chandra Babu Dara Spyros Tragoudas Themistoklis Haniotakis A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. 131-138 2011 DFT https://doi.org/10.1109/DFT.2011.13 https://doi.ieeecomputersociety.org/10.1109/DFT.2011.13 conf/dft/2011 db/conf/dft/dft2011.html#DaraTH11 Sreenivas Gangadhar Spyros Tragoudas A Probabilistic Approach to Diagnose SETs. 261-267 2011 DFT https://doi.org/10.1109/DFT.2011.19 https://doi.ieeecomputersociety.org/10.1109/DFT.2011.19 conf/dft/2011 db/conf/dft/dft2011.html#GangadharT11 Kedar Karmarkar Spyros Tragoudas Error correction encoding for multi-threshold capture mechanism. 157-162 2011 IOLTS https://doi.org/10.1109/IOLTS.2011.5993830 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2011.5993830 conf/iolts/2011 db/conf/iolts/iolts2011.html#KarmarkarT11 Luke Pierce Spyros Tragoudas Multi-level secure JTAG architecture. 208-209 2011 IOLTS https://doi.org/10.1109/IOLTS.2011.5993845 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2011.5993845 conf/iolts/2011 db/conf/iolts/iolts2011.html#PierceT11 Dheepakkumaran Jayaraman Spyros Tragoudas Occurrence probability analysis of a path at the architectural level. 464-468 2011 ISQED https://doi.org/10.1109/ISQED.2011.5770768 conf/isqed/2011 db/conf/isqed/isqed2011.html#JayaramanT11 Sreenivas Gangadhar Spyros Tragoudas An analytical method for estimating SET propagation. 197-202 2011 VTS https://doi.org/10.1109/VTS.2011.5783783 conf/vts/2011 db/conf/vts/vts2011.html#GangadharT11

Dheepakkumaran Jayaraman Rajamani Sethuram Spyros Tragoudas Scan Shift Power Reduction by Gating Internal Nodes. 311-319 2010 6 J. Low Power Electron. 2 https://doi.org/10.1166/jolpe.2010.1085 db/journals/jolpe/jolpe6.html#JayaramanST10

Michael N. Skoufis Kedar Karmarkar Spyros Tragoudas Themistoklis Haniotakis A Data Capturing Method for Buses on Chip. 1631-1641 2010 57-I IEEE Trans. Circuits Syst. I Regul. Pap. 7 https://doi.org/10.1109/TCSI.2009.2036051 db/journals/tcas/tcasI57.html#SkoufisKTH10

Rajsekhar Adapa Spyros Tragoudas Techniques to Prioritize Paths for Diagnosis. 658-661 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2009.2013469 db/journals/tvlsi/tvlsi18.html#AdapaT10

Edward Flanigan Spyros Tragoudas Identification of Delay Measurable PDFs Using Linear Dependency Relationships. 1011-1015 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2009.2017541 db/journals/tvlsi/tvlsi18.html#FlaniganT10

Kedar Karmarkar Spyros Tragoudas Scalable codeword generation for coupled buses. 729-734 2010 DATE https://doi.org/10.1109/DATE.2010.5456954 http://dl.acm.org/citation.cfm?id=1871102 conf/date/2010 db/conf/date/date2010.html#KarmarkarT10 Dheepakkumaran Jayaraman Rajamani Sethuram Spyros Tragoudas Gating internal nodes to reduce power during scan shift. 79-84 2010 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1785481.1785500 conf/glvlsi/2010 db/conf/glvlsi/glvlsi2010.html#JayaramanST10 Ashok Kumar Palaniswamy Manoj Kumar Goparaju Spyros Tragoudas Scalable identification of threshold logic functions. 269-274 2010 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1785481.1785545 https://www.wikidata.org/entity/Q130884269 conf/glvlsi/2010 db/conf/glvlsi/glvlsi2010.html#PalaniswamyGT10 Sreenivas Gangadhar Spyros Tragoudas Probabilistic methods for the impact of an SET in combinational logic. 41-46 2010 IOLTS https://doi.org/10.1109/IOLTS.2010.5560234 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560234 conf/iolts/2010 db/conf/iolts/iolts2010.html#GangadharT10 Michael N. Skoufis Spyros Tragoudas On-line detection of random voltage perturbations in buses with multiple-threshold receivers. 249-254 2010 IOLTS https://doi.org/10.1109/IOLTS.2010.5560192 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560192 conf/iolts/2010 db/conf/iolts/iolts2010.html#SkoufisT10 Sreenivas Gangadhar Spyros Tragoudas A novel probabilistic SET propagation method. 258-263 2010 ISQED https://doi.org/10.1109/ISQED.2010.5450452 conf/isqed/2010 db/conf/isqed/isqed2010.html#GangadharT10 Edward Flanigan Spyros Tragoudas Arkan Abdulrahman Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions. 140-145 2009 VTS https://doi.org/10.1109/VTS.2009.22 https://doi.ieeecomputersociety.org/10.1109/VTS.2009.22 conf/vts/2009 db/conf/vts/vts2009.html#FlaniganTA09 Dimitris Gizopoulos Susumu Horiguchi Spyros Tragoudas Mohammad Tehranipoor 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009 2009 IEEE Computer Society DFT 978-0-7695-3839-6 https://ieeexplore.ieee.org/xpl/conhome/5372211/proceeding http://www.computer.org/csdl/proceedings/dft/2009/3839/00/index.html db/conf/dft/dft2009.html

Kyriakos Christou Maria K. Michael Spyros Tragoudas On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. 203-222 2008 24 J. Electron. Test. 1-3 https://doi.org/10.1007/s10836-007-5020-8 db/journals/et/et24.html#ChristouMT08

Arkan Abdulrahman Spyros Tragoudas Low-power multi-core ATPG to target concurrency. 459-473 2008 41 Integr. 4 https://doi.org/10.1016/j.vlsi.2007.11.001 db/journals/integration/integration41.html#AbdulrahmanT08

Chunrong Song Spyros Tragoudas Identification of Critical Executable Paths at the Architectural Level. 2291-2302 2008 27 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2008.2008912 db/journals/tcad/tcad27.html#SongT08

Manoj Kumar Goparaju Ashok Kumar Palaniswamy Spyros Tragoudas A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. 176-183 2008 DFT https://doi.org/10.1109/DFT.2008.44 https://doi.ieeecomputersociety.org/10.1109/DFT.2008.44 conf/dft/2008 db/conf/dft/dft2008.html#GoparajuPT08 Rajsekhar Adapa Spyros Tragoudas Prioritization of Paths for Diagnosis. 474-481 2008 DFT https://doi.org/10.1109/DFT.2008.46 https://doi.ieeecomputersociety.org/10.1109/DFT.2008.46 conf/dft/2008 db/conf/dft/dft2008.html#AdapaT08 Sreenivas Gangadhar Michael N. Skoufis Spyros Tragoudas Propagation of Transients Along Sensitizable Paths. 129-134 2008 IOLTS https://doi.org/10.1109/IOLTS.2008.46 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2008.46 conf/iolts/2008 db/conf/iolts/iolts2008.html#GangadharST08 Rajsekhar Adapa Edward Flanigan Spyros Tragoudas A Novel Test Generation Methodology for Adaptive Diagnosis. 242-245 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479733 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.79 conf/isqed/2008 db/conf/isqed/isqed2008.html#AdapaFT08 Michael N. Skoufis Kedar Karmarkar Themistoklis Haniotakis Spyros Tragoudas A High-Performance Bus Architecture for Strongly Coupled Interconnects. 407-410 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479766 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.21 conf/isqed/2008 db/conf/isqed/isqed2008.html#SkoufisKHT08 Edward Flanigan Arkan Abdulrahman Spyros Tragoudas Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. 633-636 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479811 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.76 conf/isqed/2008 db/conf/isqed/isqed2008.html#FlaniganAT08 Dheepakkumaran Jayaraman Edward Flanigan Spyros Tragoudas Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. 1-10 2008 ITC https://doi.org/10.1109/TEST.2008.4700626 https://doi.ieeecomputersociety.org/10.1109/TEST.2008.4700626 conf/itc/2008 db/conf/itc/itc2008.html#JayaramanFT08 Manoj Kumar Goparaju Spyros Tragoudas A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. 323-328 2008 VTS https://doi.org/10.1109/VTS.2008.43 https://doi.ieeecomputersociety.org/10.1109/VTS.2008.43 conf/vts/2008 db/conf/vts/vts2008.html#GoparajuT08 Dimitri Kagaris Spyros Tragoudas Graph Theory and Algorithms. 2008 Wiley Encyclopedia of Computer Science and Engineering https://doi.org/10.1002/9780470050118.ecse531 reference/wiley/2008 db/reference/wiley/wiley2008.html#KagarisT08

Khadija Jirari Stewart Spyros Tragoudas Managing the power resources of sensor networks with performance considerations. 1122-1135 2007 30 Comput. Commun. 5 https://doi.org/10.1016/j.comcom.2006.11.008 db/journals/comcom/comcom30.html#StewartT07

Mahilchi Milir Vaseekar Kumar Spyros Tragoudas High-Quality Transition Fault ATPG for Small Delay Defects. 983-989 2007 26 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/TCAD.2007.8361591 https://doi.org/10.1109/TCAD.2006.884863 db/journals/tcad/tcad26.html#KumarT07

Michalis D. Galanis Gregory Dimitroulakos Spyros Tragoudas Costas E. Goutis Speedups in embedded systems with a high-performance coprocessor datapath. 2007 12 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/1255456.1255472 https://www.wikidata.org/entity/Q130970683 db/journals/todaes/todaes12.html#GalanisDTG07 35:1-35:22

Michael N. Skoufis Haibo Wang 0005 Themistoklis Haniotakis Spyros Tragoudas Glitch Control with Dynamic Receiver Threshold Adjustment. 410-415 2007 conf/isqed/2007 ISQED https://doi.org/10.1109/ISQED.2007.86 https://doi.ieeecomputersociety.org/10.1109/ISQED.2007.86 db/conf/isqed/isqed2007.html#SkoufisWHT07 Manoj Kumar Goparaju Spyros Tragoudas A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. 420-425 2007 conf/isqed/2007 ISQED https://doi.org/10.1109/ISQED.2007.12 https://doi.ieeecomputersociety.org/10.1109/ISQED.2007.12 db/conf/isqed/isqed2007.html#GoparajuT07 Rajsekhar Adapa Edward Flanigan Spyros Tragoudas Michael Laisne Hailong Cui Tsvetomir Petrov Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. 717-722 2007 conf/isqed/2007 ISQED https://doi.org/10.1109/ISQED.2007.81 https://doi.ieeecomputersociety.org/10.1109/ISQED.2007.81 db/conf/isqed/isqed2007.html#AdapaFTLCP07 Edward Flanigan Spyros Tragoudas Enhanced Identification of Strong Robustly Testable Paths. 729-736 2007 conf/isqed/2007 ISQED https://doi.org/10.1109/ISQED.2007.73 https://doi.ieeecomputersociety.org/10.1109/ISQED.2007.73 db/conf/isqed/isqed2007.html#FlaniganT07 Edward Flanigan Rajsekhar Adapa Hailong Cui Michael Laisne Spyros Tragoudas Tsvetomir Petrov Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. 805-812 2007 conf/vlsid/2007 VLSI Design https://doi.org/10.1109/VLSID.2007.86 https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.86 db/conf/vlsid/vlsid2007.html#FlaniganACLTP07 Rajsekhar Adapa Spyros Tragoudas Maria K. Michael Accelerating Diagnosis via Dominance Relations between Sets of Faults. 219-224 2007 conf/vts/2007 VTS https://doi.org/10.1109/VTS.2007.10 https://doi.ieeecomputersociety.org/10.1109/VTS.2007.10 db/conf/vts/vts2007.html#AdapaTM07

Dimitri Kagaris Spyros Tragoudas Sherin Kuriakose InTeRail: A Test Architecture for Core-Based SOCs. 137-149 2006 55 IEEE Trans. Computers 2 https://doi.org/10.1109/TC.2006.27 http://doi.ieeecomputersociety.org/10.1109/TC.2006.27 db/journals/tc/tc55.html#KagarisTK06

Michalis D. Galanis George Theodoridis Spyros Tragoudas Constantinos E. Goutis A high-performance data path for synthesizing DSP kernels. 1154-1162 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/TCAD.2005.855965 db/journals/tcad/tcad25.html#GalanisTTG06

Mahilchi Milir Vaseekar Kumar Spyros Tragoudas Sreejit Chakravarty Rathish Jayabharathi Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. 2954-2964 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2006.882583 db/journals/tcad/tcad25.html#KumarTCJ06

Stelios Neophytou Maria K. Michael Spyros Tragoudas Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement. 3026-3035 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2006.882635 db/journals/tcad/tcad25.html#NeophytouMT06

Saravanan Padmanaban Spyros Tragoudas Implicit grading of multiple path delay faults. 346-361 2006 11 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/1142155.1142160 db/journals/todaes/todaes11.html#PadmanabanT06

Kyriakos Christou Maria K. Michael Spyros Tragoudas Implicit Critical PDF Test Generation with Maximal Test Efficiency. 50-58 2006 conf/dft/2006 DFT https://doi.org/10.1109/DFT.2006.34 https://doi.ieeecomputersociety.org/10.1109/DFT.2006.34 db/conf/dft/dft2006.html#ChristouMT06 Sandeep Dechu Manoj Kumar Goparaju Spyros Tragoudas A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. 318-326 2006 conf/dft/2006 DFT https://doi.org/10.1109/DFT.2006.7 https://doi.ieeecomputersociety.org/10.1109/DFT.2006.7 db/conf/dft/dft2006.html#DechuGT06 Stelios Neophytou Maria K. Michael Spyros Tragoudas Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. 43-50 2006 conf/iolts/2006 IOLTS https://doi.org/10.1109/IOLTS.2006.26 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.26 db/conf/iolts/iolts2006.html#NeophytouMT06 Rajsekhar Adapa Spyros Tragoudas Maria K. Michael Sub-faults identification for collapsing in diagnosis. 2006 conf/iscas/2006 ISCAS https://doi.org/10.1109/ISCAS.2006.1692710 db/conf/iscas/iscas2006.html#AdapaTM06 Krishna Prasad Raghuraman Haibo Wang 0005 Spyros Tragoudas Minimizing FPGA Reconfiguration Data at Logic Level. 219-224 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.87 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.87 db/conf/isqed/isqed2006.html#RaghuramanWT06 Arkan Abdulrahman Spyros Tragoudas Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. 300-305 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.104 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.104 db/conf/isqed/isqed2006.html#AbdulrahmanT06 Rajsekhar Adapa Spyros Tragoudas Maria K. Michael Evaluation of Collapsing Methods for Fault Diagnosis. 439-444 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.62 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.62 db/conf/isqed/isqed2006.html#AdapaTM06 Edward Flanigan Themistoklis Haniotakis Spyros Tragoudas An Improved Method for Identifying Linear Dependencies in Path Delay Faults. 457-462 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.24 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.24 db/conf/isqed/isqed2006.html#FlaniganHT06 Mahilchi Milir Vaseekar Kumar Spyros Tragoudas Sreejit Chakravarty Rathish Jayabharathi Exact At-speed Delay Fault Grading in Sequential Circuits. 1-10 2006 ITC https://doi.org/10.1109/TEST.2006.297685 conf/itc/2006 db/conf/itc/itc2006.html#KumarTCJ06 Khadija Jirari Stewart Spyros Tragoudas Interconnect Testing for Networks on Chips. 100-107 2006 conf/vts/2006 VTS https://doi.org/10.1109/VTS.2006.41 https://doi.ieeecomputersociety.org/10.1109/VTS.2006.41 db/conf/vts/vts2006.html#StewartT06

Michalis D. Galanis George Theodoridis Spyros Tragoudas Constantinos E. Goutis A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. 877-893 2005 14 J. Circuits Syst. Comput. 4 https://doi.org/10.1142/S0218126605002659 db/journals/jcsc/jcsc14.html#GalanisTTG05

Mahilchi Milir Vaseekar Kumar Spyros Tragoudas Low Power Test Generation for Path Delay Faults. 194-205 2005 1 J. Low Power Electron. 2 https://doi.org/10.1166/jolpe.2005.019 db/journals/jolpe/jolpe1.html#KumarT05

Saravanan Padmanaban Spyros Tragoudas Efficient identification of (critical) testable path delay faults using decision diagrams. 77-87 2005 24 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/TCAD.2004.839488 db/journals/tcad/tcad24.html#PadmanabanT05

Spyros Tragoudas Vijay Nagarandal On-chip embedding mechanisms for large sets of vectors for delay test. 488-497 2005 24 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2004.842800 db/journals/tcad/tcad24.html#TragoudasN05

M. Moiz Khan Spyros Tragoudas Rewiring for watermarking digital circuit netlists. 1132-1137 2005 24 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2005.850855 db/journals/tcad/tcad24.html#KhanT05

Maria K. Michael Spyros Tragoudas Function-based compact test pattern generation for path delay faults. 996-1001 2005 13 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2005.853607 db/journals/tvlsi/tvlsi13.html#MichaelT05

Mahilchi Milir Vaseekar Kumar Spyros Tragoudas Sreejit Chakravarty Rathish Jayabharathi Implicit and Exact Path Delay Fault Grading in Sequential Circuits. 990-995 2005 conf/date/2005 DATE https://doi.org/10.1109/DATE.2005.179 https://doi.ieeecomputersociety.org/10.1109/DATE.2005.179 http://dl.acm.org/citation.cfm?id=1049260 db/conf/date/date2005.html#KumarTCJ05 Khadija Jirari Stewart Themistoklis Haniotakis Spyros Tragoudas A security protocol for sensor networks. 5 2005 GLOBECOM https://doi.org/10.1109/GLOCOM.2005.1577964 conf/globecom/2005 db/conf/globecom/globecom2005.html#StewartHT05 Mahilchi Milir Vaseekar Kumar Spyros Tragoudas Low power test generation for path delay faults using stability functions. 8-12 2005 conf/glvlsi/2005 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1057661.1057666 db/conf/glvlsi/glvlsi2005.html#KumarT05 Stelios Neophytou Maria K. Michael Spyros Tragoudas Test set enhancement for quality transition faults using function-based methods. 182-187 2005 conf/glvlsi/2005 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1057661.1057706 db/conf/glvlsi/glvlsi2005.html#NeophytouMT05 Maria K. Michael Kyriakos Christou Spyros Tragoudas Towards finding path delay fault tests with high test efficiency using ZBDDs. 464-467 2005 conf/iccd/2005 ICCD https://doi.org/10.1109/ICCD.2005.109 https://doi.ieeecomputersociety.org/10.1109/ICCD.2005.109 db/conf/iccd/iccd2005.html#MichaelCT05 Mahilchi Milir Vaseekar Kumar Spyros Tragoudas Quality Transition Fault Tests Suitable for Small Delay Defects. 468-470 2005 conf/iccd/2005 ICCD https://doi.org/10.1109/ICCD.2005.88 https://doi.ieeecomputersociety.org/10.1109/ICCD.2005.88 db/conf/iccd/iccd2005.html#KumarT05 Khadija Jirari Stewart Themistoklis Haniotakis Spyros Tragoudas Design and Evaluation of a Security Scheme for Sensor Networks. 197-201 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.39 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.39 db/conf/isqed/isqed2005.html#StewartHT05 M. Welling Spyros Tragoudas Haibo Wang 0005 A Minimum Cut Based Re-Synthesis Approach. 202-207 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.9 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.9 db/conf/isqed/isqed2005.html#WellingTW05 Themistoklis Haniotakis Spyros Tragoudas G. Pani Reduced Test Application Time Based on Reachability Analysis. 232-237 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.102 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.102 db/conf/isqed/isqed2005.html#HaniotakisTP05 Maria K. Michael Stelios Neophytou Spyros Tragoudas Functions for Quality Transition Fault Tests. 327-332 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.60 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.60 db/conf/isqed/isqed2005.html#MichaelNT05 Krishna Prasad Raghuraman Haibo Wang 0005 Spyros Tragoudas A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs. 673-676 2005 conf/vlsid/2005 VLSI Design https://doi.org/10.1109/ICVD.2005.25 https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.25 db/conf/vlsid/vlsid2005.html#RaghuramanWT05

Maria K. Michael Themistoklis Haniotakis Spyros Tragoudas A unified framework for generating all propagation functions for logic errors and events. 980-986 2004 23 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/TCAD.2004.828112 db/journals/tcad/tcad23.html#MichaelHT04

J. V. Deodhar Spyros Tragoudas Implicit deductive fault simulation for complex delay fault models. 636-641 2004 12 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2004.827598 db/journals/tvlsi/tvlsi12.html#DeodharT04

Saravanan Padmanaban Spyros Tragoudas Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. 50-55 2004 conf/date/2004 DATE https://doi.org/10.1109/DATE.2004.1268826 https://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268826 http://dl.acm.org/citation.cfm?id=969026 db/conf/date/date2004-1.html#PadmanabanT04 Michalis D. Galanis George Theodoridis Spyros Tragoudas Dimitrios Soudris Constantinos E. Goutis Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. 275-276 2004 conf/fccm/2004 FCCM https://doi.org/10.1109/FCCM.2004.11 https://doi.ieeecomputersociety.org/10.1109/FCCM.2004.11 db/conf/fccm/fccm2004.html#GalanisTTSG04 Michalis D. Galanis George Theodoridis Spyros Tragoudas Dimitrios Soudris Constantinos E. Goutis A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. 252 2004 conf/fpga/2004 FPGA https://doi.org/10.1145/968280.968337 db/conf/fpga/fpga2004.html#GalanisTTSG04 Michalis D. Galanis George Theodoridis Spyros Tragoudas Dimitrios Soudris Constantinos E. Goutis Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. 868-873 https://doi.org/10.1007/978-3-540-30117-2_91 2004 conf/fpl/2004 FPL db/conf/fpl/fpl2004.html#GalanisTTSG04 Mahilchi Milir Vaseekar Kumar Saravanan Padmanaban Spyros Tragoudas Low power ATPG for path delay faults. 389-392 2004 conf/glvlsi/2004 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/988952.989046 db/conf/glvlsi/glvlsi2004.html#KumarPT04 Themistoklis Haniotakis Spyros Tragoudas Constantinos Kalapodas Security enhancement through multiple path transmission in ad hoc networks. 4187-4191 2004 ICC https://doi.org/10.1109/ICC.2004.1313337 conf/icc/2004 db/conf/icc/icc2004.html#HaniotakisTK04 Michalis D. Galanis George Theodoridis Spyros Tragoudas Dimitrios Soudris Costas E. Goutis A high performance data-path to accelerate DSP kernels. 495-498 2004 ICECS https://doi.org/10.1109/ICECS.2004.1399726 conf/icecsys/2004 db/conf/icecsys/icecsys2004.html#GalanisTTSG04 M. Moiz Khan Spyros Tragoudas Rewiring for Watermarking Digital Circuits. 143-148 2004 conf/isqed/2004 ISQED https://doi.org/10.1109/ISQED.2004.1283665 https://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283665 db/conf/isqed/isqed2004.html#KhanT04 Saravanan Padmanaban Spyros Tragoudas An Adaptive Path Delay Fault Diagnosis Methodology. 491-496 2004 conf/isqed/2004 ISQED https://doi.org/10.1109/ISQED.2004.1283721 https://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283721 db/conf/isqed/isqed2004.html#PadmanabanT04 Saravanan Padmanaban Spyros Tragoudas A Critical Path Selection Method for Delay Testing. 232-241 2004 conf/itc/2004 ITC https://doi.org/10.1109/TEST.2004.1386957 https://doi.ieeecomputersociety.org/10.1109/ITC.2004.8 db/conf/itc/itc2004.html#PadmanabanT04 Haibo Wang 0005 Suchitra Kulkarni Spyros Tragoudas On-line Testing Field Programmable Analog Array Circuits. 1340-1348 2004 conf/itc/2004 ITC https://doi.org/10.1109/TEST.2004.1387409 https://doi.ieeecomputersociety.org/10.1109/ITC.2004.132 db/conf/itc/itc2004.html#WangKT04 Arkan Abdulrahman Spyros Tragoudas Compact ATPG for Concurrent SOC Testing. 16-21 2004 conf/mtv/2004 MTV https://doi.org/10.1109/MTV.2004.6 https://doi.ieeecomputersociety.org/10.1109/MTV.2004.6 db/conf/mtv/mtv2004.html#AbdulrahmanT04 M. Moiz Khan Spyros Tragoudas Magdy S. Abadir Jiang Brandon Liu Identification of Gates for Covering all Critical Paths. 92-96 2004 conf/mtv/2004 MTV https://doi.org/10.1109/MTV.2004.15 https://doi.ieeecomputersociety.org/10.1109/MTV.2004.15 db/conf/mtv/mtv2004.html#KhanTAL04 Michalis D. Galanis George Theodoridis Spyros Tragoudas Dimitrios Soudris Constantinos E. Goutis Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. 652-661 https://doi.org/10.1007/978-3-540-30205-6_67 2004 conf/patmos/2004 PATMOS db/conf/patmos/patmos2004.html#GalanisTTSG04 Michalis D. Galanis George Theodoridis Spyros Tragoudas Dimitrios Soudris Costas E. Goutis A Novel Data-Path for Accelerating DSP Kernels. 363-372 https://doi.org/10.1007/978-3-540-27776-7_38 2004 conf/samos/2004 SAMOS db/conf/samos/samos2004.html#GalanisTTSG04

Dimitri Kagaris Spyros Tragoudas LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds. 233-244 2003 19 J. Electron. Test. 3 https://doi.org/10.1023/A:1023740811613 db/journals/et/et19.html#KagarisT03

Saravanan Padmanaban Maria K. Michael Spyros Tragoudas Exact path delay fault coverage with fundamental ZBDD operations. 305-316 2003 22 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2002.807891 db/journals/tcad/tcad22.html#PadmanabanMT03

Saravanan Padmanaban Spyros Tragoudas An implicit path-delay fault diagnosis methodology. 1399-1408 2003 22 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2003.818132 db/journals/tcad/tcad22.html#PadmanabanT03

Spyros Tragoudas N. Denny Path delay fault testing using test points. 1-10 2003 8 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/606603.606604 db/journals/todaes/todaes8.html#TragoudasD03

Saravanan Padmanaban Spyros Tragoudas Non-Enumerative Path Delay Fault Diagnosis . 10322-10327 2003 conf/date/2003 DATE https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10012 http://dl.acm.org/citation.cfm?id=1022745 db/conf/date/date2003.html#PadmanabanT03 Dimitri Kagaris Spyros Tragoudas InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs. 219-224 2003 conf/iolts/2003 IOLTS https://doi.org/10.1109/OLT.2003.1214402 https://doi.ieeecomputersociety.org/10.1109/OLT.2003.1214402 db/conf/iolts/iolts2003.html#KagarisT03 Maria K. Michael Spyros Tragoudas Generation of Hazard Identification Functions. 419-424 2003 conf/isqed/2003 ISQED https://doi.org/10.1109/ISQED.2003.1194769 https://doi.ieeecomputersociety.org/10.1109/ISQED.2003.1194769 db/conf/isqed/isqed2003.html#MichaelT03

Turgay Korkmaz Marwan Krunz Spyros Tragoudas An efficient algorithm for finding a path subject to two additive constraints. 225-238 2002 25 Comput. Commun. 3 https://doi.org/10.1016/S0140-3664(01)00358-9 https://www.wikidata.org/entity/Q127586939 db/journals/comcom/comcom25.html#KorkmazKT02

Dimitrios Kagaris Spyros Tragoudas Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. 305-313 2002 18 J. Electron. Test. 3 https://doi.org/10.1023/A:1015087206329 db/journals/et/et18.html#KagarisT02

Spyros Tragoudas Yaakov L. Varol Disjoint Paths with Length Constraints. 158-166 2002 9 Int. J. Comput. Their Appl. 3 db/journals/isca/isca9.html#TragoudasV02

Xrysovalantis Kavousianos Dimitris Bakalis Dimitris Nikolos Spyros Tragoudas A new built-in TPG method for circuits with random patternresistant faults. 859-866 2002 21 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2002.1013898 db/journals/tcad/tcad21.html#KavousianosBNT02

Dimitrios Kagaris Spyros Tragoudas On the nonenumerative path delay fault simulation problem. 1095-1101 2002 21 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/TCAD.2002.801108 db/journals/tcad/tcad21.html#KagarisT02

Maria K. Michael Spyros Tragoudas ATPG tools for delay faults at the functional level. 33-57 2002 7 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/504914.504916 db/journals/todaes/todaes7.html#MichaelT02

Saravanan Padmanaban Spyros Tragoudas Exact Grading of Multiple Path Delay Faults. 84-88 2002 conf/date/2002 DATE https://doi.org/10.1109/DATE.2002.998253 https://doi.ieeecomputersociety.org/10.1109/DATE.2002.998253 http://dl.acm.org/citation.cfm?id=874363 db/conf/date/date2002.html#PadmanabanT02

Dimitrios Kagaris Spyros Tragoudas Computational analysis of counter-based schemes for VLSI test pattern generation. 227-250 2001 110 Discret. Appl. Math. 2-3 db/journals/dam/dam110.html#KagarisT01 https://doi.org/10.1016/S0166-218X(00)00259-6 https://www.wikidata.org/entity/Q127517107

Dimitrios Kagaris Spyros Tragoudas Von Neumann hybrid cellular automata for generating deterministic test sequences. 308-321 2001 6 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/383251.383254 db/journals/todaes/todaes6.html#KagarisT01

Spyros Tragoudas The most reliable data-path transmission. 281-285 2001 50 IEEE Trans. Reliab. 3 https://doi.org/10.1109/24.974124 db/journals/tr/tr50.html#Tragoudas01

Dimitri Kagaris Spyros Tragoudas Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. 75-79 2001 conf/iolts/2001 IOLTW https://doi.org/10.1109/OLT.2001.937822 https://doi.ieeecomputersociety.org/10.1109/OLT.2001.937822 db/conf/iolts/ioltw2001.html#KagarisT01 Jayant Deodhar Spyros Tragoudas Color Counting and its Application to Path Delay Fault Coverage. 378-383 2001 conf/isqed/2001 ISQED https://doi.org/10.1109/ISQED.2001.915259 https://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915259 db/conf/isqed/isqed2001.html#DeodharT01 Maria K. Michael Spyros Tragoudas ATPG for Path Delay Faults without Path Enumeration. 384-389 2001 conf/isqed/2001 ISQED https://doi.org/10.1109/ISQED.2001.915260 https://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915260 db/conf/isqed/isqed2001.html#MichaelT01 Saravanan Padmanaban Maria K. Michael Spyros Tragoudas Exact path delay grading with fundamental BDD operations. 642-651 2001 conf/itc/2001 ITC db/conf/itc/itc2001.html#PadmanabanMT01 https://doi.org/10.1109/TEST.2001.966684 https://doi.ieeecomputersociety.org/10.1109/TEST.2001.966684

Dimitri Kagaris Spyros Tragoudas Amitava Majumdar 0002 Test-set partitioning for multi-weighted random LFSRs. 65-75 2000 30 Integr. 1 https://doi.org/10.1016/S0167-9260(00)00010-9 db/journals/integration/integration30.html#KagarisTM00

Dimitrios Kagaris Spyros Tragoudas Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. 42-47 2000 conf/iccd/2000 ICCD https://doi.org/10.1109/ICCD.2000.878267 https://doi.ieeecomputersociety.org/10.1109/ICCD.2000.878267 db/conf/iccd/iccd2000.html#KagarisT00 Dimitri Kagaris Spyros Tragoudas Methods for on-chip embedding of path delay test vectors. 84-87 2000 ISCAS https://doi.org/10.1109/ISCAS.2000.857032 conf/iscas/2000 db/conf/iscas/iscas2000.html#KagarisT00 Turgay Korkmaz Marwan Krunz Spyros Tragoudas An efficient algorithm for finding a path subject to two additive constraints. 318-327 2000 conf/sigmetrics/2000 SIGMETRICS https://doi.org/10.1145/339331.339427 https://doi.org/10.1145/345063.339427 db/conf/sigmetrics/sigmetrics2000.html#KorkmazKT00 Spyros Tragoudas Power dissipation component of a management protocol for ad-hoc networks. 555-559 2000 WCNC https://doi.org/10.1109/WCNC.2000.903913 conf/wcnc/2000 db/conf/wcnc/wcnc2000.html#Tragoudas00 Spyros Tragoudas S. Dimitrova Routing with energy considerations in mobile ad-hoc networks. 1258-1261 2000 WCNC https://doi.org/10.1109/WCNC.2000.904812 conf/wcnc/2000 db/conf/wcnc/wcnc2000.html#TragoudasD00

Dimitri Kagaris Spyros Tragoudas Maximum weighted independent sets on transitive graphs and applications1. 77-86 1999 27 Integr. 1 https://doi.org/10.1016/S0167-9260(98)00017-0 https://www.wikidata.org/entity/Q127344056 db/journals/integration/integration27.html#KagarisT99

Dimitrios Kagaris Grammati E. Pantziou Spyros Tragoudas Christos D. Zaroliagis Transmissions in a network with capacities and delays. 167-174 1999 33 Networks 3 https://doi.org/10.1002/(SICI)1097-0037(199905)33:3<167::AID-NET2>3.0.CO;2-J db/journals/networks/networks33.html#KagarisPTZ99

Dimitrios Kagaris Spyros Tragoudas On the design of optimal counter-based schemes for test set embedding. 219-230 1999 18 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/43.743738 db/journals/tcad/tcad18.html#KagarisT99

Spyros Tragoudas Dimitrios Karayiannis A fast nonenumerative automatic test pattern generator for pathdelay faults. 1050-1057 1999 18 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/43.771185 db/journals/tcad/tcad18.html#TragoudasK99

Spyros Tragoudas Ralf Münzenberger Kenneth J. Danhof Board-level partitioning for partial scan using fuzzy logic. 241-249 1999 7 IEEE Trans. Fuzzy Syst. 2 https://doi.org/10.1109/91.755405 db/journals/tfs/tfs7.html#TragoudasMD99

Spyros Tragoudas Yaakov L. Varol Disjoint paths with length constraints. 277-280 1999 conf/cata/1999 CATA db/conf/cata/cata1999.html#TragoudasV99 Spyros Tragoudas Maria K. Michael ATPG Tools for Delay Faults at the Functional Level. 631- 1999 conf/date/1999 DATE https://doi.org/10.1109/DATE.1999.761195 https://doi.ieeecomputersociety.org/10.1109/DATE.1999.761195 https://doi.org/10.1145/307418.307578 db/conf/date/date1999.html#TragoudasM99 Spyros Tragoudas N. Denny Testing for Path Delay Faults Using Test Points. 86-94 1999 conf/dft/1999 DFT https://doi.org/10.1109/DFTVS.1999.802873 https://doi.ieeecomputersociety.org/10.1109/DFTVS.1999.802873 db/conf/dft/dft1999.html#TragoudasD99 Dimitrios Kagaris Spyros Tragoudas LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. 130-138 1999 conf/dft/1999 DFT https://doi.org/10.1109/DFTVS.1999.802878 https://doi.ieeecomputersociety.org/10.1109/DFTVS.1999.802878 db/conf/dft/dft1999.html#KagarisT99 Spyros Tragoudas Maria K. Michael Functional ATPG for Delay Faults. 16-19 1999 conf/glvlsi/1999 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1999.757367 https://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757367 db/conf/glvlsi/glvlsi1999.html#TragoudasM99 Spyros Tragoudas The most reliable data path transmission. 15-19 1999 conf/ipccc/1999 IPCCC https://doi.org/10.1109/PCCC.1999.749415 db/conf/ipccc/ipccc1999.html#Tragoudas99 Dimitrios Kagaris Spyros Tragoudas Embedded cores using built-in mechanisms. 23-26 1999 conf/iscas/1999 ISCAS (1) https://doi.org/10.1109/ISCAS.1999.777796 db/conf/iscas/iscas1999-1.html#KagarisT99 Spyros Tragoudas Accurate path delay fault coverage is feasible. 201-210 1999 conf/itc/1999 ITC db/conf/itc/itc1999.html#Tragoudas99 https://doi.org/10.1109/TEST.1999.805631 https://doi.ieeecomputersociety.org/10.1109/TEST.1999.805631 Spyros Tragoudas CAD Tools for BIST/DFT and Delay Faults. 1999 The VLSI Handbook https://doi.org/10.1201/9781420049671.ch68 reference/vlsi/1999 db/reference/vlsi/vlsi1999.html#Tragoudas99

Dimitrios Karayiannis Spyros Tragoudas Clustering Network Modules with Different Implementations for Delay Minimization. 1-13 1998 7 VLSI Design 1 https://doi.org/10.1155/1998/69289 db/journals/vlsi/vlsi7.html#KarayiannisT98

Dimitrios Karayiannis Spyros Tragoudas Timing-Driven Circuit Implementation. 211-224 1998 7 VLSI Design 2 https://doi.org/10.1155/1998/49145 db/journals/vlsi/vlsi7.html#KarayiannisT98a

Dimitrios Kagaris Spyros Tragoudas Amitava Majumdar 0002 On-Chip Test Embedding for Multi-Weighted Random LFSRs. 135- 1998 conf/dft/1998 DFT https://doi.org/10.1109/DFTVS.1998.732160 https://doi.ieeecomputersociety.org/10.1109/DFTVS.1998.732160 db/conf/dft/dft1998.html#KagarisTM98 Dimitrios Karayiannis Spyros Tragoudas A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults. 440-445 1998 conf/vts/1998 VTS https://doi.org/10.1109/VTEST.1998.670908 https://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670908 db/conf/vts/vts1998.html#KarayiannisT98

Spyros Tragoudas Dimitrios Karayiannis Implementing and clustering modules with complex delays. 39-57 1997 22 Integr. 1-2 https://doi.org/10.1016/S0167-9260(97)00004-7 db/journals/integration/integration22.html#TragoudasK97

Dimitrios Kagaris Spyros Tragoudas Dimitrios Karayiannis Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. 309-315 1997 16 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/43.594836 db/journals/tcad/tcad16.html#KagarisTK97

Dimitrios Kagaris Spyros Tragoudas Cellular automata for generating deterministic test sequences. 77-81 1997 ED&TC https://doi.org/10.1109/EDTC.1997.582336 https://doi.ieeecomputersociety.org/10.1109/EDTC.1997.582336 https://dl.acm.org/doi/10.5555/787260.787653 conf/date/1997 db/conf/date/edtc1997.html#KagarisT97 Dimitrios Kagaris Spyros Tragoudas Maximum independent sets on transitive graphs and their applications in testing and CAD. 736-740 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643620 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643620 https://dl.acm.org/citation.cfm?id=266624 db/conf/iccad/iccad1997.html#KagarisT97 Dimitrios Kagaris Spyros Tragoudas Dimitrios Karayiannis Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms. 366-371 1997 conf/iccd/1997 ICCD db/conf/iccd/iccd97.html#KagarisTK97 https://doi.org/10.1109/ICCD.1997.628896 https://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628896

Spyros Tragoudas Improved Approximations for the Minimum-Cut Ratio and the Flux. 157-167 1996 29 Math. Syst. Theory 2 db/journals/mst/mst29.html#Tragoudas96 https://doi.org/10.1007/BF01305312

Dimitrios Kagaris Spyros Tragoudas Retiming-Based Partial Scan. 75-87 1996 45 IEEE Trans. Computers 1 db/journals/tc/tc45.html#KagarisT96 https://doi.org/10.1109/12.481488 http://doi.ieeecomputersociety.org/10.1109/12.481488

Spyros Tragoudas Min-Cut Partitioning on Underlying Tree and Graph Structures. 470-474 1996 45 IEEE Trans. Computers 4 db/journals/tc/tc45.html#Tragoudas96 https://doi.org/10.1109/12.494104 http://doi.ieeecomputersociety.org/10.1109/12.494104

Dimitrios Kagaris Spyros Tragoudas Amitava Majumdar 0002 On the Use of Counters for Reproducing Deterministic Test Sets. 1405-1419 1996 45 IEEE Trans. Computers 12 db/journals/tc/tc45.html#KagarisTM96 https://doi.org/10.1109/12.545970 http://doi.ieeecomputersociety.org/10.1109/12.545970

Dimitrios Kagaris Spyros Tragoudas A fast algorithm for minimizing FPGA combinational and sequential modules. 341-351 1996 1 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/234860.234863 db/journals/todaes/todaes1.html#KagarisT96

Dimitrios Kagaris Spyros Tragoudas Amitava Majumdar 0002 Deterministic Test Pattern Reproduction by a Counter. 37-41 1996 ED&TC https://doi.org/10.1109/EDTC.1996.494125 https://doi.ieeecomputersociety.org/10.1109/EDTC.1996.494125 https://dl.acm.org/doi/10.5555/787259.787552 conf/date/1996 db/conf/date/edtc1996.html#KagarisTM96 Dimitrios Kagaris Spyros Tragoudas A multiseed counter TPG with performance guarantee. 34-39 1996 conf/iccd/1996 ICCD https://doi.org/10.1109/ICCD.1996.563528 https://doi.ieeecomputersociety.org/10.1109/ICCD.1996.563528 db/conf/iccd/iccd1996.html#KagarisT96 D. Kuguris Spyros Tragoudas FPGA Module Minimization. 566-571 1996 conf/iccd/1996 ICCD https://doi.org/10.1109/ICCD.1996.563607 https://doi.ieeecomputersociety.org/10.1109/ICCD.1996.563607 db/conf/iccd/iccd1996.html#KugurisT96 Dimitrios Karayiannis Spyros Tragoudas ATPD: An Automatic Test Pattern Generator for Path Delay Faults. 443-452 1996 conf/itc/1996 ITC db/conf/itc/itc1996.html#KarayiannisT96 https://doi.org/10.1109/TEST.1996.557051 https://doi.ieeecomputersociety.org/10.1109/TEST.1996.557051 Dimitrios Kagaris Spyros Tragoudas Generating deterministic unordered test patterns with counters. 374-379 1996 conf/vts/1996 VTS https://doi.org/10.1109/VTEST.1996.510881 https://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510881 db/conf/vts/vts1996.html#KagarisT96 Spyros Tragoudas Yaakov L. Varol Computing Disjoint Path with Lenght Constraints. 375-389 1996 conf/wg/1996 WG db/conf/wg/wg96.html#TragoudasV96 https://doi.org/10.1007/3-540-62559-3_30

Dimitrios Kagaris Spyros Tragoudas Avoiding linear dependencies in LFSR test pattern generators. 229-241 1995 6 J. Electron. Test. 2 https://doi.org/10.1007/BF00993089 https://www.wikidata.org/entity/Q114694122 db/journals/et/et6.html#KagarisT95

James Haralambides Spyros Tragoudas Bipartitioning into Overlapping Sets. 67-88 1995 6 Int. J. Found. Comput. Sci. 1 db/journals/ijfcs/ijfcs6.html#HaralambidesT95 https://doi.org/10.1142/S0129054195000068

Frank Thomson Leighton Fillia Makedon Serge A. Plotkin Clifford Stein 0001 Éva Tardos Spyros Tragoudas Fast Approximation Algorithms for Multicommodity Flow Problems. 228-243 1995 50 J. Comput. Syst. Sci. 2 db/journals/jcss/jcss50.html#LeightonMPSST95 https://doi.org/10.1006/jcss.1995.1020

Dimitrios Kagaris Spyros Tragoudas Dinesh Bhatia Pseudo-exhaustive built-in TPG for sequential circuits. 1160-1171 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/43.406718 db/journals/tcad/tcad14.html#KagarisTB95

Dimitrios Karayiannis Spyros Tragoudas Uniform area timing-driven circuit implementation. 2-7 1995 conf/glvlsi/1995 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1995.516015 https://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516015 http://dl.acm.org/citation.cfm?id=797377 db/conf/glvlsi/glvlsi1995.html#KarayiannisT95 Dimitrios Kagaris Spyros Tragoudas Grammati E. Pantziou Christos D. Zaroliagis Quickest paths: parallelization and dynamization . 39-40 1995 conf/hicss/1995 HICSS (2) https://doi.org/10.1109/HICSS.1995.375479 https://doi.ieeecomputersociety.org/10.1109/HICSS.1995.375479 db/conf/hicss/hicss1995.html#KagarisTPZ95 Dimitrios Kagaris Spyros Tragoudas Grammati E. Pantziou Christos D. Zaroliagis On the Computation of Fast Data Transmissions in Networks with Capacities and Delays. 291-302 1995 conf/wads/1995 WADS db/conf/wads/wads95.html#KagarisTPZ95 https://doi.org/10.1007/3-540-60220-8_71

James Haralambides Spyros Tragoudas The Problem of Partitioning with Duplications and its Applications. 395-406 1994 3 Int. J. Artif. Intell. Tools 3 https://doi.org/10.1142/S0218213094000224 db/journals/ijait/ijait3.html#HaralambidesT94

Dimitrios Kagaris Fillia Makedon Spyros Tragoudas A method for pseudo-exhaustive test pattern generation. 1170-1178 1994 13 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/43.310906 db/journals/tcad/tcad13.html#KagarisMT94

Spyros Tragoudas On Channel Routing Problems With Interchangeable Terminals. 51-68 1994 2 VLSI Design 1 https://doi.org/10.1155/1994/48137 db/journals/vlsi/vlsi2.html#Tragoudas94

Dinesh Bhatia Amit Chowdhary Spyros Tragoudas Mathematical model for routability analysis of FPGAs. 76-79 1994 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1994.289992 conf/glvlsi/1994 db/conf/glvlsi/glvlsi1994.html#BhatiaCT94 Dimitrios Kagaris Spyros Tragoudas Retiming algorithms with application to VLSI testability. 216-221 1994 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1994.289966 conf/glvlsi/1994 db/conf/glvlsi/glvlsi1994.html#KagarisT94 Spyros Tragoudas An improved algorithm for the generalized min-cut partitioning problem. 242-247 1994 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1994.289961 conf/glvlsi/1994 db/conf/glvlsi/glvlsi1994.html#Tragoudas94 Dimitrios Kagaris Spyros Tragoudas A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators. 292-295 1994 conf/iccd/1994 ICCD db/conf/iccd/iccd1994.html#KagarisT94 https://doi.org/10.1109/ICCD.1994.331908 https://doi.ieeecomputersociety.org/10.1109/ICCD.1994.331908 Jim E. Crenshaw Spyros Tragoudas Naveed A. Sherwani High Performance Over-the-Cell Routing. 137-142 1994 conf/vlsid/1994 VLSI Design db/conf/vlsid/vlsid1994.html#CrenshawTS94 https://doi.org/10.1109/ICVD.1994.282672 https://doi.ieeecomputersociety.org/10.1109/ICVD.1994.282672 Dimitrios Kagaris Spyros Tragoudas A design for testability technique for test pattern generation with LFSRs. 68-73 1994 VTS https://doi.org/10.1109/VTEST.1994.292332 https://doi.ieeecomputersociety.org/10.1109/VTEST.1994.292332 conf/vts/1994 db/conf/vts/vts1994.html#KagarisT94

Antonios Symvonis Spyros Tragoudas Searching a Pseudo 3-Sided Solid Orthoconvex Grid. 325-353 1993 4 Int. J. Found. Comput. Sci. 4 db/journals/ijfcs/ijfcs4.html#SymvonisT93 https://doi.org/10.1142/S0129054193000213

Spyros Tragoudas Ioannis G. Tollis River routing and density minimization for channels with interchangeable terminals. 151-178 1993 15 Integr. 2 https://doi.org/10.1016/0167-9260(93)90050-M db/journals/integration/integration15.html#TragoudasT93

Dimitrios Kagaris Spyros Tragoudas Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets. 526-536 1993 1 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/92.250200 db/journals/tvlsi/tvlsi1.html#KagarisT93

Dimitrios Kagaris Spyros Tragoudas Partial Scan with Retiming. 249-254 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164881 db/conf/dac/dac93.html#KagarisT93 Spyros Tragoudas Minmax-cut graph partitioning problems. 100-104 1993 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1993.224471 conf/glvlsi/1993 db/conf/glvlsi/glvlsi1993.html#Tragoudas93 Dimitrios Kagaris Spyros Tragoudas Dinesh Bhatia Pseudoexhaustive BIST for Sequential Circuits. 523-527 1993 conf/iccd/1993 ICCD db/conf/iccd/iccd1993.html#KagarisTB93 https://doi.org/10.1109/ICCD.1993.393322 https://doi.ieeecomputersociety.org/10.1109/ICCD.1993.393322 Fillia Makedon Spyros Tragoudas Approximate solutions for Graph and Hypergraph Partitioning. 133-166 1993 Algorithmic Aspects of VLSI Layout https://doi.org/10.1142/9789812794468_0004 books/ws/93/SL1993 db/books/collections/SL1993.html#MakedonT93

Spyros Tragoudas Fillia Makedon Robert Farell Circuit partitioning into small sets. 481-491 1992 16 Microprocess. Microsystems 9 https://doi.org/10.1016/0141-9331(92)90109-7 db/journals/mam/mam16.html#TragoudasMF92

Dimitrios Kagaris Fillia Makedon Spyros Tragoudas On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability. 358-364 1992 conf/iccd/1992 ICCD db/conf/iccd/iccd1992.html#KagarisMT92 https://doi.org/10.1109/ICCD.1992.276289 https://doi.ieeecomputersociety.org/10.1109/ICCD.1992.276289 Antonios Symvonis Spyros Tragoudas Searching a Solid Pseudo 3-Sided Orthoconvex Grid. 188-197 1992 conf/isaac/1992 ISAAC db/conf/isaac/isaac92.html#SymvonisT92 https://doi.org/10.1007/3-540-56279-6_72

Panayiotis E. Pintelas Spyros Tragoudas A comparative study of five language independent programming environments. 3-15 1991 14 J. Syst. Softw. 1 https://doi.org/10.1016/0164-1212(91)90084-J db/journals/jss/jss14.html#PintelasT91

Spyros Tragoudas R. Farrell Fillia Makedon Circuit partitioning into small sets: a tool to support testing with further applications. 518-522 1991 EURO-DAC http://dl.acm.org/citation.cfm?id=951626 conf/eurodac/1991 db/conf/eurodac/euro-dac1991.html#TragoudasFM91 Fast Approximation Algorithms for Multicommodity Flow Problems Frank Thomson Leighton Fillia Makedon Serge A. Plotkin Clifford Stein 0001 Éva Tardos Spyros Tragoudas 101-111 conf/stoc/STOC23 1991 STOC db/conf/stoc/stoc91.html#LeightonMPSTT91 https://doi.org/10.1145/103418.103425 Fillia Makedon Spyros Tragoudas Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems. 140-153 1990 conf/wg/1990 WG db/conf/wg/wg90.html#MakedonT90 https://doi.org/10.1007/3-540-53832-1_39 Magdy S. Abadir Khader S. Abdel-Hafez Arkan Abdulrahman Rajsekhar Adapa Wisam Aljubouri Phaninder Alladi Iraklis Anagnostopoulos Dimitris Bakalis Dinesh Bhatia Sreejit Chakravarty Xiaoqian Chen Amit Chowdhary Kyriakos Christou Jim E. Crenshaw Hailong Cui Krishna Dahal Kenneth J. Danhof Chandra Babu Dara Sandeep Dechu N. Denny J. V. Deodhar Jayant Deodhar Grigoris DimitroulakosGregory Dimitroulakos S. Dimitrova Robert Farell R. Farrell Rezoan Ferdous Edward Flanigan Michalis D. Galanis Sreenivas Gangadhar Dimitris Gizopoulos Krishna Prasad Gnawali Manoj Kumar Goparaju Constantinos E. GoutisCostas E. Goutis Kiriti Nagesh Gowda Lalit Gupta Themistoklis Haniotakis James Haralambides Susumu Horiguchi Yao Hu Aashish Itani Pavan Kumar Javvaji Rathish Jayabharathi Dheepakkumaran Jayaraman Iresh M. Jayawardana Shengbing Jiang Dimitrios KagarisDimitri Kagaris Constantinos Kalapodas Andreas Karatzas Dimitrios Karayiannis Kedar Karmarkar Xrysovalantis Kavousianos M. Moiz Khan Nasser Khdeer Ganesh Kondapuram Turgay Korkmaz Marwan Krunz D. Kuguris Suchitra Kulkarni Mahilchi Milir Vaseekar Kumar Sherin Kuriakose Michael Laisne Frank Thomson Leighton Stefan Leitner Joseph Lenox Jiang Brandon Liu Amitava Majumdar 0002 Fillia Makedon Danuka Malinda Maria K. Michael Pragyan P. MohantyPragyan (Sheela) Mohanty Seyed Nima Mozaffari Venkata Naresh Mudhireddy Ralf Münzenberger Vijay Nagarandal Stelios Neophytou Dimitris Nikolos Saravanan Padmanaban Ashok Kumar Palaniswamy G. Pani Aikaterini Maria Panteleaki Grammati E. Pantziou Varatheepan Paramanayakam Bijay Raj Paudel Vasileios Pentsos Tsvetomir Petrov Luke Pierce Panayiotis E. Pintelas Serge A. Plotkin Krishna Prasad Raghuraman Omkar Rijal Puneet Ramesh Savanur Mike Schmit Danushka Senarathna Rajamani Sethuram Basim Shanyour Naveed A. Sherwani Michael N. Skoufis Ahish Mysore Somashekar Chunrong Song Dimitrios Soudris Clifford Stein 0001 Khadija Jirari Stewart Antonios Symvonis Éva Tardos Mark TehranipoorMohammad Tehranipoor George Theodoridis Ioannis G. Tollis Theodoros Toulas Yaakov L. Varol Haibo Wang 0005 Adam Watkins M. Welling Jason Wibbenmeyer Chinthana Wimalasuriya Christos D. Zaroliagis