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Minoru Saeki
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2010 – 2019
- 2016
- [j8]Takeshi Sugawara
, Daisuke Suzuki, Minoru Saeki:
Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1323-1333 (2016) - 2015
- [c5]Takeshi Sugawara
Two Operands of Multipliers in Side-Channel Attack. COSADE 2015: 64-78 - [i3]Takeshi Sugawara
Two Operands of Multipliers in Side-Channel Attack. IACR Cryptol. ePrint Arch. 2015: 291 (2015) - 2014
- [j7]Takeshi Sugawara
On measurable side-channel leaks inside ASIC design primitives. J. Cryptogr. Eng. 4(1): 59-73 (2014) - 2013
- [c4]Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino:
On Measurable Side-Channel Leaks Inside ASIC Design Primitives. CHES 2013: 159-178 - [i2]Takeshi Sugawara
On Measurable Side-Channel Leaks inside ASIC Design Primitives. IACR Cryptol. ePrint Arch. 2013: 579 (2013) - 2011
- [j6]Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Tsutomu Matsumoto:
How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 200-210 (2011) - 2010
- [j5]Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto:
A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2497-2508 (2010)
2000 – 2009
- 2009
- [c3]Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh:
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. CHES 2009: 189-204 - 2008
- [j4]Minoru Saeki, Daisuke Suzuki:
Security Evaluations of MRSL and DRSL Considering Signal Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 176-183 (2008) - [j3]Daisuke Suzuki, Minoru Saeki:
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 184-192 (2008) - 2007
- [j2]Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa:
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 160-168 (2007) - [j1]Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa:
Leakage Analysis of DPA Countermeasures at the Logic Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 169-178 (2007) - 2006
- [c2]Daisuke Suzuki, Minoru Saeki:
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. CHES 2006: 255-269 - 2005
- [c1]Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa:
DPA Leakage Models for CMOS Logic Circuits. CHES 2005: 366-382 - 2004
- [i1]Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa:
Random Switching Logic: A Countermeasure against DPA based on Transition Probability. IACR Cryptol. ePrint Arch. 2004: 346 (2004)
Coauthor Index
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