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Wei-Chou Hsu
2020 – today
- 2024
- [j4]Jian-Hong Ke
, Ching-Sung Lee
, Han-Yin Liu
, Jung-Hui Tsai
, Wei-Chou Hsu:
Investigations on In₀.₁₂Al₀.₈₈N/AlN/AlₓGa₁-ₓN/In₀.₁₂Al₀.₈₈N MOS-HFETs With Symmetrically-Graded Wide-Gap Channel and Drain Field-Plate Design. IEEE Access 12: 50177-50183 (2024) - 2023
- [c4]W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu:
MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. ESSDERC 2023: 9-12 - 2020
- [c3]Yi-Ping Huang, Ching-Sung Lee, Wei-Chou Hsu:
Normally-Off InAlN/GaN Fin-MOSHEMT with Fluorine Treatment. DRC 2020: 1-2
2010 – 2019
- 2015
- [c2]Ya-Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou-Ying Cheng:
6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. ISQED 2015: 610-614 - 2012
- [j3]Yi-Bo Liao, Meng-Hsueh Chiang, Keunwoo Kim, Wei-Chou Hsu:
Assessment of structure variation in silicon nanowire FETs and impact on SRAM. Microelectron. J. 43(5): 300-304 (2012) - [j2]Yang-Ching Lin, Yean-Kuo Luo, Ke-Horng Chen
, Wei-Chou Hsu:
Liquid Crystal Display (LCD) Supplied by Highly Integrated Dual-Side Dual-Output Switched-Capacitor DC-DC Converter With Only Two Flying Capacitors. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(2): 439-446 (2012) - 2010
- [j1]Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai:
Low power design of phase-change memory based on a comprehensive model. IET Comput. Digit. Tech. 4(4): 285-292 (2010)
2000 – 2009
- 2008
- [c1]Yean-Kuo Luo, Ke-Horng Chen
, Wei-Chou Hsu:
A dual-phase charge pump regulator with nano-ampere switched-capacitor CMOS voltage reference for achieving low output ripples. ICECS 2008: 446-449
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last updated on 2024-05-06 20:24 CEST by the dblp team
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