A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs - Lama Shaer; Rouwaida Kanj; Rajiv V. Joshi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs - Lama Shaer; Rouwaida Kanj; Rajiv V. Joshi; Ali Chehab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs - Lama Shaer; Rouwaida Kanj; Rajiv V. Joshi (IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, 2019)

Regularized logistic regression for fast importance sampling based SRAM yield analysis - Lama Shaer; Rouwaida Kanj; Rajiv V. Joshi; Maria Malik; Ali Chehab (18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, CA, USA, March 14-15, 2017, 2017)

Low-power digital signal processor design for a hearing aid - Lama Shaer; Ihab Nahlus; Jawad Merhi; Ayman I. Kayssi; Ali Chehab (4th Annual International Conference on Energy Aware Computing Systems and Applications, ICEAC 2013, Istanbul, Turkey, December 16-18, 2013, 2013)

Low-power adder design techniques for noise-tolerant applications - Ihab Nahlus; Lama Shaer; Ali Chehab; Ayman I. Kayssi; Mohammad M. Mansour (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2011, October 4-7, 2011, Beirut, Lebanon, 2011)