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Kazuyuki Nakamura
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2020 – today
- 2024
- [i3]Tsuyoshi Ishizone, Masaki Miyasaka, Sae Ochi, Norio Tada, Kazuyuki Nakamura:
Aortic root landmark localization with optimal transport loss for heatmap regression. CoRR abs/2407.04921 (2024) - 2023
- [j14]Hiroshi Koyama
, Hisashi Okumura
Effective mechanical potential of cell-cell interaction explains three-dimensional morphologies during early embryogenesis. PLoS Comput. Biol. 19(8) (2023) - 2022
- [j13]Tsuyoshi Ishizone, Kazuyuki Nakamura
Real-time Linear Operator Construction and State Estimation with the Kalman Filter. J. Inf. Process. 30: 888-897 (2022) - [c15]Tsuyoshi Ishizone, Tomoyuki Higuchi, Kosuke Okusa, Kazuyuki Nakamura
An Online System of Detecting Anomalies and Estimating Cycle Times for Production Lines. IECON 2022: 1-6 - [c14]Hisashi Oshima, Tsuyoshi Ishizone, Kazuyuki Nakamura
Occupancy Detection for General Households by Bidirectional LSTM with Attention. IECON 2022: 1-7 - 2021
- [i2]Yu Han, Kazuyuki Nakamura:
The Application of Zig-Zag Sampler in Sequential Markov Chain Monte Carlo. CoRR abs/2111.10210 (2021) - 2020
- [c13]Kazue Suzuki, Masaki Shimomura, Kazuyuki Nakamura, Naohiko Hirasawa, Hironori Yabuki, Takashi Yamanouchi, Terumasa Tokunaga:
Identifying Snowfall Clouds at Syowa Station, Antarctica via a Convolutional Neural Network. JSAI 2020: 73-83 - [i1]Tsuyoshi Ishizone, Tomoyuki Higuchi, Kazuyuki Nakamura:
Ensemble Kalman Variational Objectives: Nonlinear Latent Trajectory Inference with A Hybrid of Variational Inference and Ensemble Kalman Filter. CoRR abs/2010.08729 (2020)
2010 – 2019
- 2018
- [c12]Takeshi Hori, Kazuyuki Nakamura
Multiresolutional Hierarchical Bayesian NMF for Detailed Audio Analysis of Music Performances. APSIPA 2018: 1626-1635 - 2017
- [c11]Takeshi Hori, Kazuyuki Nakamura
Music chord recognition from audio data using bidirectional encoder-decoder LSTMs. APSIPA 2017: 1312-1315 - 2012
- [c10]Yoshihiro Yura, Misako Takayasu, Hideki Takayasu, Kazuyuki Nakamura:
Instability caused by the cubic potential in the foreign exchange market observed at the intervention by the Bank of Japan. FUSION 2012: 2147-2153 - [c9]Yoshito Ohya, Kazuyuki Nakamura
Extraction of groove feelings from drum data using non-negative matrix factorization. SCIS&ISIS 2012: 125-130 - 2011
- [j12]Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura:
An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O. IEICE Trans. Electron. 94-C(6): 945-952 (2011) - [c8]Kazuyuki Nakamura, Shinya Yamamoto, Makoto Honda:
Sequential data assimilation in geotechnical engineering and its application to seepage analysis. FUSION 2011: 1-6 - 2010
- [c7]Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura:
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function. ASP-DAC 2010: 365-366 - [c6]Takayuki Shibata, Kazuyuki Nakamura, Takanobu Sato, Rentaro Yoshioka:
A Knowledge Sharing System for Software Developers. ICSOFT (2) 2010: 499-503
2000 – 2009
- 2009
- [c5]Kazuyuki Nakamura, Ryo Yoshida, Masao Nagasaki, Satoru Miyano, Tomoyuki Higuchi:
Parameter Estimation of In Silico Biological Pathways with Particle Filtering Towards a Petascale Computing. Pacific Symposium on Biocomputing 2009: 227-238 - 2007
- [j11]Kazuyuki Nakamura
A Recursive Recomputation Approach for Smoothing in Nonlinear State-Space Modeling: An Attempt for Reducing Space Complexity. IEEE Trans. Signal Process. 55(11): 5167-5178 (2007) - 2006
- [j10]Kazuyuki Nakamura, Tomoyuki Higuchi, Naoki Hirose:
Sequential Data Assimilation: Information Fusion of a Numerical Simulation and Large Scale Observation Data. J. Univers. Comput. Sci. 12(6): 608-626 (2006) - 2005
- [c4]Keiichi Funaki, Kazuyuki Nakamura:
An Improvement of ITU-T G.711 Packet Loss Concealment. EuroIMSA 2005: 482-485 - 2001
- [j9]Kouichi Yamaguchi, Muneo Fukaishi, Takehiko Sakamoto, Naoto Akiyama, Kazuyuki Nakamura:
A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture. IEEE J. Solid State Circuits 36(11): 1666-1672 (2001) - [c3]Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina:
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC 2001: 213-216 - [c2]Takashi Yoshikawa, Ichiro Hatakeyama, Kazunori Miyoshi, Kazuhiko Kurata, Juni-Ichi Sasaki, Nobuharu Kami, Takara Sugimoto, Muneo Fukaishi, Kazuyuki Nakamura, Kei Tanaka, Hiroaki Nishi
Optical interconnection as an IP macro of a CMOS library. Hot Interconnects 2001: 31-35 - [c1]Takeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura:
Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations. ISLPED 2001: 305-309 - 2000
- [j8]Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi:
A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays. IEEE J. Solid State Circuits 35(11): 1611-1618 (2000)
1990 – 1999
- 1998
- [j7]Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi:
A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture. IEEE J. Solid State Circuits 33(12): 2139-2147 (1998) - 1997
- [j6]Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto:
A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. IEEE J. Solid State Circuits 32(11): 1758-1765 (1997) - 1996
- [j5]Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits 31(11): 1610-1617 (1996) - [j4]Yoshihiro Fujita, Nobuyuki Yamashita, Tohru Kimura, Kazuyuki Nakamura, Shin'ichiro Okazaki:
A 3.84 gips integrated memory array processor. Syst. Comput. Jpn. 27(3): 26-36 (1996) - 1995
- [j3]Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina:
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits 30(6): 637-643 (1995) - 1994
- [j2]Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. IEEE J. Solid State Circuits 29(11): 1317-1322 (1994) - [j1]Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina:
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. IEEE J. Solid State Circuits 29(11): 1336-1343 (1994)
Coauthor Index
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