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Vinicius S. Livramento
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2020 – today
- 2022
- [j5]Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, Laleh Behjat, José Luís Güntzel:
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1481-1494 (2022)
2010 – 2019
- 2019
- [j4]Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1147-1160 (2019) - [c15]Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, José Luís Güntzel:
How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization. ISPD 2019: 3-10 - 2018
- [c14]Sheiny Fabre, José Luís Güntzel, Laércio Lima Pilla, Renan Netto, Tiago Fontana, Vinicius S. Livramento:
Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning. SBCCI 2018: 1-6 - 2017
- [j3]Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Incremental Layer Assignment Driven by an External Signoff Timing Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1126-1139 (2017) - [c13]Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. DAC 2017: 18:1-18:6 - [c12]Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan:
Concurrent Pin Access Optimization for Unidirectional Routing. DAC 2017: 20:1-20:6 - [c11]Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla, José Luís Güntzel:
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library. ISPD 2017: 25-31 - [c10]Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel:
Exploiting cache locality to speedup register clustering. SBCCI 2017: 191-197 - 2016
- [j2]Vinicius S. Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz Cláudio Villar dos Santos:
Clock-Tree-Aware Incremental Timing-Driven Placement. ACM Trans. Design Autom. Electr. Syst. 21(3): 38:1-38:27 (2016) - [c9]Renan Netto, Chrystian Guth, Vinicius S. Livramento, Márcio Castro, Laércio Lima Pilla, José Luís Güntzel:
Exploiting parallelism to speed up circuit legalization. ICECS 2016: 624-627 - [c8]Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel:
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. ISVLSI 2016: 36-41 - [c7]Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel:
Evaluating the impact of circuit legalization on incremental optimization techniques. SBCCI 2016: 1-6 - 2015
- [c6]Vinicius S. Livramento, Chrystian Guth, Renan Netto, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization. ICCAD 2015: 528-535 - [c5]Chrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos:
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. ISPD 2015: 141-148 - 2014
- [j1]Vinicius S. Livramento, Chrystian Guth, José Luís Almada Güntzel, Marcelo O. Johann:
A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation. ACM Trans. Design Autom. Electr. Syst. 19(4): 40:1-40:25 (2014) - 2013
- [c4]Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann:
Fast and efficient lagrangian relaxation-based discrete gate sizing. DATE 2013: 1855-1860 - 2012
- [c3]Vinicius dos S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann:
Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization. ICECS 2012: 468-471 - 2011
- [c2]Vinicius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Güntzel:
An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices. ISCAS 2011: 587-590 - [c1]Vinicius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Almada Güntzel:
An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms. SBCCI 2011: 149-154
Coauthor Index
aka: José Luís Almada Güntzel
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