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Mario Garrido
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2020 – today
- 2024
- [j35]Zeynep Kaya
, Mario Garrido
Optimized 4-Parallel 1024-Point MSC FFT. IEEE Access 12: 84110-84121 (2024) - [c18]Zeynep Kaya
Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs. ARITH 2024: 52-59 - 2023
- [j34]Guang-Ting Deng, Mario Garrido
Radix-2k MSC FFT Architectures. IEEE Access 11: 81497-81510 (2023) - [j33]Víctor Manuel Bautista
Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3992-4003 (2023) - [j32]Zeynep Kaya
Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 4004-4014 (2023) - [j31]Zeynep Kaya
Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3084-3088 (2023) - [j30]Pedro Paz
CORDIC-Based Computation of Arcsine and Arccosine Functions on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3684-3688 (2023) - [j29]Pedro Paz
Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices. J. Signal Process. Syst. 95(4): 543-550 (2023) - [c17]Víctor Manuel Bautista, Mario Garrido:
An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond. DCIS 2023: 1-6 - [c16]Pedro Paz, Mario Garrido:
A 5.2-GS/s 8-Parallel 1024-Point MDC FFT. DCIS 2023: 1-6 - [c15]Charalampos Eleftheriadis
Energy-Efficient Short-Time Fourier Transform for Partial Window Overlapping. ISCAS 2023: 1-5 - 2022
- [j28]Mario Garrido
Simplifying Karnaugh Maps by Making Groups of Non-power-of-two Elements. Circuits Syst. Signal Process. 41(10): 5895-5902 (2022) - [j27]Mario Garrido
A Survey on Pipelined FFT Hardware Architectures. J. Signal Process. Syst. 94(11): 1345-1364 (2022) - 2021
- [j26]Mario Garrido
The Constant Multiplier FFT. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 322-335 (2021) - [j25]Mario Garrido
Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 1003-1007 (2021) - 2020
- [j24]Mario Garrido
Continuous-Flow Matrix Transposition Using Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3035-3046 (2020) - [j23]Rikard Andersson, Mario Garrido
Using Rotator Transformations to Simplify FFT Hardware Architectures. IEEE Trans. Circuits Syst. 67-I(12): 4784-4793 (2020) - [j22]Narges Mohammadi Sarband
Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems. J. Signal Process. Syst. 92(10): 1075-1089 (2020) - [c14]Mario Garrido
Evolution of the Performance of Pipelined FFT Architectures Through the Years. DCIS 2020: 1-6 - [c13]Shun-Che Hsu, Shen-Jui Huang, Sau-Gee Chen, Shin-Che Lin, Mario Garrido
A 128-Point Multi-Path SC FFT Architecture. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j21]Mario Garrido
Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal. IEEE Trans. Circuits Syst. II Express Briefs 66-II(4): 657-661 (2019) - [j20]Mario Garrido
World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1507-1516 (2019) - [j19]Hans Kanders, Tobias Mellqvist
A 1 Million-Point FFT on a Single FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3863-3873 (2019) - [j18]Mario Garrido
Optimum Circuits for Bit-Dimension Permutations. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1148-1160 (2019) - [c12]Nanda K. Unnikrishnan
Effect of Finite Word-Length on SQNR, Area and Power for Real-Valued Serial FFT. ISCAS 2019: 1-5 - 2018
- [j17]Konrad Möller
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 710-714 (2018) - [j16]Mario Garrido
Feedforward FFT Hardware Architectures Based on Rotator Allocation. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 581-592 (2018) - [j15]Martin Kumm, Oscar Gustafsson
Optimal Single Constant Multiplication Using Ternary Adders. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 928-932 (2018) - [j14]Mario Garrido
A Serial Commutator Fast Fourier Architecture for Real-Valued Signals. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1693-1697 (2018) - [j13]Mario Garrido
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations. J. Signal Process. Syst. 90(11): 1581-1582 (2018) - [c11]Cheolyong Bae
Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters. ACSSC 2018: 213-217 - [c10]Narges Mohammadi Sarband, Oscar Gustafsson
Obtaining Minimum Depth Sum of Products from Multiple Constant Multiplication. SiPS 2018: 134-139 - 2017
- [j12]Mario Garrido
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 375-379 (2017) - [c9]Anton Kovalev, Oscar Gustafsson
Implementation approaches for 512-tap 60 GSa/s chromatic dispersion FIR filters. ACSSC 2017: 1779-1783 - 2016
- [j11]Mario Garrido
CORDIC II: A New Improved CORDIC Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 186-190 (2016) - [j10]Mario Garrido
The Feedforward Short-Time Fourier Transform. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 868-872 (2016) - [j9]Mario Garrido
The Serial Commutator FFT. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 974-978 (2016) - [j8]Mario Garrido
A New Representation of FFT Algorithms Using Triangular Matrices. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1737-1745 (2016) - [j7]Mario Garrido
Multiplierless Unity-Gain SDF FFTs. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 3003-3007 (2016) - 2014
- [j6]Mario Garrido
Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI). IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2002-2012 (2014) - [j5]Sau-Gee Chen, Shen-Jui Huang, Mario Garrido
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2869-2877 (2014) - [c8]Mario Garrido
Challenging the limits of FFT performance on FPGAs (Invited paper). ISIC 2014: 172-175 - 2013
- [j4]Mario Garrido
Pipelined Radix-2k Feedforward FFT Architectures. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 23-32 (2013) - [c7]Padma Prasad Boopal, Mario Garrido
A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards. ISCAS 2013: 2066-2070 - 2012
- [c6]Petter Kallstrom, Mario Garrido
Low-complexity rotators for the FFT using base-3 signed stages. APCCAS 2012: 519-522 - 2011
- [j3]Mario Garrido
Optimum Circuits for Bit Reversal. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 657-661 (2011) - [j2]Mario Garrido
Accurate Rotations Based on Coefficient Scaling. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 662-666 (2011) - [c5]Tanvir Ahmed
A 512-point 8-parallel pipelined feedforward FFT for WPAN. ACSCC 2011: 981-984 - [c4]Jesús Grajal, Omar A. Yeste Ojeda, Miguel Angel Sánchez, Mario Garrido, Marisa López-Vallejo:
Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications. EUSIPCO 2011: 1514-1518 - 2010
- [c3]Fahad Qureshi, Mario Garrido
Alternatives for low-complexity complex rotators. ICECS 2010: 17-20
2000 – 2009
- 2009
- [j1]Mario Garrido
A Pipelined FFT Architecture for Real-Valued Signals. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(12): 2634-2643 (2009) - 2007
- [c2]Mario Garrido
Efficient Memoryless Cordic for FFT Computation. ICASSP (2) 2007: 113-116 - 2006
- [c1]Miguel A. Sánchez Marcos, Mario Garrido
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation. FPT 2006: 127-134
Coauthor Index
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last updated on 2024-08-05 20:23 CEST by the dblp team
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