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Michael Riepen
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2010 – 2019
- 2012
- [c6]Isaías A. Comprés Ureña, Michael Riepen, Michael Konow, Michael Gerndt:
Invasive MPI on Intel's Single-Chip Cloud Computer. ARCS 2012: 74-85 - [c5]Pablo Reble, Carsten Clauss, Michael Riepen, Stefan Lankes, Thomas Bemmerl:
Connecting the Cloud: Transparent and Flexible Communication for a Cluster of Intel SCCs. MARC@RWTH 2012: 13-19 - [c4]Hans C. Woithe, William Brozas, Christian Wills, Bharath Pichai, Ulrich Kremer, Mike Eichhorn, Michael Riepen:
Enabling Computation Intensive Applications in Battery-Operated Cyber-Physical Systems. MARC Symposium 2012: 34-39 - 2011
- [j2]Matthias Gries
, Ulrich Hoffmann, Michael Konow, Michael Riepen:
SCC: A Flexible Architecture for Many-Core Platform Research. Comput. Sci. Eng. 13(6): 79-83 (2011) - [j1]Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46(1): 173-183 (2011) - [c3]Isaías A. Comprés Ureña, Michael Riepen, Michael Konow:
RCKMPI - Lightweight MPI Implementation for Intel's Single-chip Cloud Computer (SCC). EuroMPI 2011: 208-217 - 2010
- [c2]Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC 2010: 108-109 - [c1]Timothy G. Mattson, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram R. Vangal, Nitin Borkar, Gregory Ruhl, Saurabh Dighe:
The 48-core SCC Processor: the Programmer's View. SC 2010: 1-11
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