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Christos A. Papachristou
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- affiliation: Case Western Reserve University, USA
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2020 – today
- 2024
- [i4]Paul Whitten, Francis G. Wolff, Christos A. Papachristou:
An AI Architecture with the Capability to Explain Recognition Results. CoRR abs/2406.08740 (2024) - [i3]Paul Whitten
, Francis G. Wolff, Christos A. Papachristou:
An AI Architecture with the Capability to Classify and Explain Hardware Trojans. CoRR abs/2407.04551 (2024) - 2023
- [j25]Abdelsalam Al Share
Design of High Speed BCD Adder Using CMOS Technology. IEEE Access 11: 141628-141639 (2023) - [c126]Paul Whitten
Explainable Neural Network Recognition of Handwritten Characters. CCWC 2023: 176-182 - 2020
- [c125]Francis G. Wolff, Daniel J. Weyer, Christos A. Papachristou
Design Space Exploration Driven by Lifetime Concerns due to Electromigration. ISQED 2020: 73-80
2010 – 2019
- 2019
- [c124]Daniel J. Weyer, Francis G. Wolff, Christos A. Papachristou
Methodology for Tradeoffs between Performance and Lifetimes of Integrated Circuits. IOLTS 2019: 60-63 - 2015
- [j24]Osama Daifallah Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel
Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication. J. Circuits Syst. Comput. 24(2): 1550019:1-1550019:21 (2015) - [c123]Maryam S. Hashemian, Bhanu Pratap Singh, Francis G. Wolff, Daniel J. Weyer, Steve Clay, Christos A. Papachristou:
A robust authentication methodology using physically unclonable functions in DRAM arrays. DATE 2015: 647-652 - 2014
- [c122]Arunprasath Shankar, Bhanu Pratap Singh, Francis G. Wolff, Christos A. Papachristou
Ontology-guided Conceptual Analysis of Design Specifications. DAC 2014: 34:1-34:6 - [c121]Bhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Steve Clay:
Cross-correlation of specification and RTL for soft IP analysis. DATE 2014: 1-6 - [c120]Bhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Daniel J. Weyer, Christos A. Papachristou
Knowledge-Guided Methodology for Third-Party Soft IP Analysis. VLSID 2014: 246-251 - 2013
- [j23]Osama Daifallah Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel
High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic. Microprocess. Microsystems 37(3): 287-298 (2013) - [j22]Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis. IEEE Trans. Computers 62(11): 2183-2195 (2013) - [c119]Lawrence Leinweber, Bhanu Pratap Singh, Christos A. Papachristou
Expert System Simulation of Hardware. ICTAI 2013: 207-212 - [c118]Arunprasath Shankar, Bhanu Pratap Singh, Francis G. Wolff, Christos A. Papachristou
NEFCIS: Neuro-fuzzy Concept Based Inference System for Specification Mining. ICTAI 2013: 337-343 - [c117]Bhanu Pratap Singh, Arunprasath Shankar, Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou
Knowledge-Guided Methodology for Specification Analysis. ICTAI 2013: 749-754 - [c116]Yuriy Shiyanovskii, Christos A. Papachristou
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs. ISQED 2013: 24-29 - 2012
- [c115]Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou
A low power memory cell design for SEU protection against radiation effects. AHS 2012: 288-295 - [c114]Lawrence Leinweber, Christos A. Papachristou
An efficient elliptic curve cryptography processor using addition chains with high information entropy. CCECE 2012: 1-6 - 2011
- [j21]Huthaifa Al-Omari, Christos A. Papachristou, Francis G. Wolff, David R. McIntyre:
Smoothing delay jitter in networked control systems. J. Embed. Comput. 4(1): 11-21 (2011) - [c113]Lawrence Leinweber, Christos A. Papachristou
An analysis of efficient formulas for elliptic curve point addition over binary extension fields. CISS 2011: 1-5 - [c112]Osama Daifallah Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel
Fast and compact binary-to-BCD conversion circuits for decimal multiplication. ICCD 2011: 226-231 - [c111]Osama Daifallah Al-Khaleel, Mohammad Al-Khaleel
Fast binary/decimal adder/subtractor with a novel correction-free BCD addition. ICECS 2011: 455-459 - [c110]Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou
A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS. IOLTS 2011: 139-144 - [c109]Aravind Rajendran, Yuriy Shiyanovskii, Frank Wolff, Christos A. Papachristou
Noise margin, critical charge and power-delay tradeoffs for SRAM design. IOLTS 2011: 145-150 - 2010
- [c108]Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis G. Wolff, Christos A. Papachristou
System level self-healing for parametric yield and reliability improvement under power bound. AHS 2010: 52-58 - [c107]Yuriy Shiyanovskii, Francis G. Wolff, Aravind Rajendran, Christos A. Papachristou
Process reliability based trojans through NBTI and HCI effects. AHS 2010: 215-222 - [c106]Francis G. Wolff, Christos A. Papachristou
Embedded system protection from software corruption. AHS 2010: 223-229 - [c105]Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST 2010: 13-18 - [c104]David R. McIntyre, Francis G. Wolff, Christos A. Papachristou
Trustworthy computing in a multi-core system using distributed scheduling. IOLTS 2010: 211-213
2000 – 2009
- 2009
- [c103]Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou
An Adaptable Task Manager for Reconfigurable Architecture Kernels. AHS 2009: 132-137 - [c102]Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou
MERO: A Statistical Approach for Hardware Trojan Detection. CHES 2009: 396-410 - [c101]Huthaifa Al-Omari, Francis G. Wolff, Christos A. Papachristou
Avoiding Delay Jitter in Cyber-Physical Systems Using One Way Delay Variations Model. CSE (2) 2009: 295-302 - [c100]David R. McIntyre, Francis G. Wolff, Christos A. Papachristou
Dynamic Evaluation of Hardware Trust. HOST 2009: 108-111 - [c99]Lawrence Leinweber, Christos A. Papachristou
Efficient architectures for elliptic curve cryptography processors for RFID. ICCD 2009: 372-377 - [c98]Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou
SRAM cell design using tri-state devices for SEU protection. IOLTS 2009: 114-119 - [c97]Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou:
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS 2009: 129 - [c96]Huthaifa Al-Omari, Francis G. Wolff, Christos A. Papachristou
An Improved Algorithm to Smooth Delay Jitter in Cyber-Physical Systems. ScalCom-EmbeddedCom 2009: 81-86 - [i2]Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, W. Clay:
Hardware Trojan by Hot Carrier Injection. CoRR abs/0906.3832 (2009) - [i1]Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, W. Clay:
Exploiting Semiconductor Properties for Hardware Trojans. CoRR abs/0906.3834 (2009) - 2008
- [c95]Gorn Tepvorachai, Christos A. Papachristou
Face Recognition using a Cognitive Processing Model. AHS 2008: 505-512 - [c94]Francis G. Wolff, Christos A. Papachristou
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. DATE 2008: 1362-1365 - [c93]Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou
A high-speed radix-4 multiplexer-based array multiplier. ACM Great Lakes Symposium on VLSI 2008: 115-118 - [c92]Francis G. Wolff, Christos A. Papachristou
An Embedded Flash Memory Vault for Software Trojan Protection. HOST 2008: 97-99 - [c91]Gorn Tepvorachai, Christos A. Papachristou
Multi-label imbalanced data enrichment process in neural net classifier training. IJCNN 2008: 1301-1307 - [c90]Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou
SRAM Cell Design Protected from SEU Upsets. IOLTS 2008: 169-170 - 2007
- [c89]Gorn Tepvorachai, Christos A. Papachristou
A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure. AHS 2007: 176-183 - [c88]Gorn Tepvorachai, Christos A. Papachristou
Facial Image Associative Memory Model. AHS 2007: 233-242 - [c87]Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff:
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA. DATE 2007: 1460-1465 - [c86]Osama Daifallah Al-Khaleel, Christos A. Papachristou
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. IOLTS 2007: 71-78 - 2006
- [j20]Hani Rizk, Christos A. Papachristou
A Self Test Program Design Technique for Embedded DSP Cores. J. Electron. Test. 22(1): 71-87 (2006) - [j19]Shih-Yu Yang, Christos A. Papachristou
A method for detecting interconnect DSM defects in systems on chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 197-204 (2006) - [c85]Gorn Tepvorachai, Christos A. Papachristou
Self-Configurable Neural Network Processor for FIR Filter Applications. AHS 2006: 114-121 - [c84]Osama Daifallah Al-Khaleel, Christos A. Papachristou
A Large Scale Adaptable Multiplier for Cryptographic Applications. AHS 2006: 477-484 - [c83]Balkaran S. Gill, Christos A. Papachristou
Soft delay error analysis in logic circuits. DATE 2006: 47-52 - [c82]Christos A. Papachristou
A Dynamic Reconfigurable Fabric for Platform SoCs. FPL 2006: 1-4 - [c81]Osama Daifallah Al-Khaleel, Christos A. Papachristou
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. ICCD 2006: 314-319 - 2005
- [c80]Balkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories. DATE 2005: 592-597 - [c79]Jianchun Li, Christos A. Papachristou, Raj Shekhar:
Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only). FPGA 2005: 279 - [c78]Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou
Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. IOLTS 2005: 266-271 - [c77]Balkaran S. Gill, Christos A. Papachristou
Node sensitivity analysis for soft errors in CMOS logic. ITC 2005: 9 - 2004
- [c76]Francis G. Wolff, Christos A. Papachristou
Test Compression and Hardware Decompression for Scan-Based SoCs. DATE 2004: 716-717 - [c75]Hani Rizk, Christos A. Papachristou
Designing Self Test Programs for Embedded DSP Cores. DATE 2004: 816-823 - [c74]Jianchun Li, Christos A. Papachristou, Raj Shekhar:
A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing. FCCM 2004: 320-321 - [c73]Jianchun Li, Christos A. Papachristou, Raj Shekhar:
A "Brick" Caching Scheme for 3D Medical Imaging. ISBI 2004: 563-566 - [c72]Balkaran S. Gill, Christos A. Papachristou
Soft Delay Error Effects in CMOS Combinational Circuits. VTS 2004: 325-334 - 2003
- [c71]Michael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre:
A Technique for High Ratio LZW Compression. DATE 2003: 10116-10121 - 2002
- [j18]Mehrdad Nourani, Christos A. Papachristou
False path exclusion in delay analysis of RTL structures. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 30-43 (2002) - [c70]Francis G. Wolff, Christos A. Papachristou:
Multiscan-Based Test Compression and Hardware Decompression Using LZ77. ITC 2002: 331-339 - 2001
- [j17]Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
Integrated test of interacting controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. 6(3): 401-422 (2001) - [c69]Kelly A. Ockunzzi, Christos A. Papachristou:
Test Strategies for BIST at the Algorithmic and Register-Transfer Levels. DAC 2001: 65-70 - [c68]Shih-Yu Yang, Christos A. Papachristou
Improving Bus Test Via IDDT and Boundary Scan. DAC 2001: 307-312 - [c67]Chien-Hua Tsai, Christos A. Papachristou
Detection of text strings from mixed text/graphics images. Document Recognition and Retrieval 2001: 201-211 - [c66]Kelly A. Ockunzzi, Christos A. Papachristou:
Breaking Correlation to Improve Testability. VTS 2001: 75-81 - 2000
- [j16]Mehrdad Nourani, Christos A. Papachristou
Stability-based algorithms for high-level synthesis of digital ASICs. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 431-435 (2000) - [c65]Mehrdad Nourani, Joan Carletta, Christos A. Papachristou:
Synthesis-for-testability of controller-datapath pairs that use gated clocks. DAC 2000: 613-618 - [c64]Joan Carletta, Christos A. Papachristou
Detecting Undetectable Controller Faults Using Power Analysis. DATE 2000: 723-728 - [c63]Mehrdad Nourani, Christos A. Papachristou:
An ILP formulation to optimize test access mechanism in system-on-chip testing. ITC 2000: 902-910
1990 – 1999
- 1999
- [j15]Mehrdad Nourani, Christos A. Papachristou
Structural Fault Testing of Embedded Cores Using Pipelining. J. Electron. Test. 15(1-2): 129-144 (1999) - [j14]Christos A. Papachristou
A multiple clocking scheme for low-power RTL design. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 266-276 (1999) - [c62]Francis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou:
Using codesign techniques to support analog functionality. CODES 1999: 79-84 - [c61]Christos A. Papachristou
Microprocessor Based Testing for Core-Based System on Chip. DAC 1999: 586-591 - [c60]Joan Carletta, Mehrdad Nourani, Christos A. Papachristou
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. DATE 1999: 278-282 - [c59]Christos A. Papachristou
A Method of Distributed Controller Design for RTL Circuits. DATE 1999: 774-775 - [c58]Christos A. Papachristou:
High Time for Higher Level BIST. ITC 1999: 1117 - [c57]Ken Batcher, Christos A. Papachristou:
Instruction Randomization Self Test For Processor Cores. VTS 1999: 34-40 - 1998
- [j13]Christos A. Papachristou
High-Level Test Synthesis for Behavioral and Structural Designs. J. Electron. Test. 13(2): 167-188 (1998) - [j12]Kelly A. Ockunzzi, Christos A. Papachristou
Testability Enhancement for Control-Flow Intensive Behaviors. J. Electron. Test. 13(3): 239-257 (1998) - [c56]Wei Zhao, Christos A. Papachristou
Testing DSP Cores Based on Self-Test Programs. DATE 1998: 166-172 - [c55]Mehrdad Nourani, Christos A. Papachristou
A Bypass Scheme for Core-Based System Fault Testing. DATE 1998: 979-980 - [c54]Mehrdad Nourani, Christos A. Papachristou:
Parallelism in Structural Fault Testing of Embedded Cores. VTS 1998: 15-21 - 1997
- [j11]Joan Carletta, Christos A. Papachristou
Behavioral Testability Insertion for Datapath/Controller Circuits. J. Electron. Test. 11(1): 9-28 (1997) - [c53]Kowen Lai, Christos A. Papachristou, Mikhail Baklashov:
BIST testability enhancement using high level test synthesis for behavioral and structural designs. Asian Test Symposium 1997: 338-342 - [c52]Mehrdad Nourani, Joan Carletta, Christos A. Papachristou:
A Scheme for Integrated Controller-Datapath Fault Testing. DAC 1997: 546-551 - [c51]Mehrdad Nourani, Christos A. Papachristou
Structural BIST insertion using behavioral test analysis. ED&TC 1997: 64-68 - [c50]Christos A. Papachristou, Mikhail Baklashov:
A test synthesis technique using redundant register transfers. ICCAD 1997: 414-420 - [c49]Kowen Lai, Christos A. Papachristou, Mikhail Baklashov:
High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains. ICCD 1997: 636-641 - [c48]Kelly A. Ockunzzi, Christos A. Papachristou:
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements. ITC 1997: 236-245 - 1996
- [c47]Kowen Lai, Christos A. Papachristou:
BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design. Asian Test Symposium 1996: 219- - [c46]Ehat Ercanli, Christos A. Papachristou:
A Register File and Scheduling Model for Application Specific Processor Synthesis. DAC 1996: 35-40 - [c45]Christos A. Papachristou
An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. DAC 1996: 337-342 - [c44]Wei Zhao, Christos A. Papachristou
An evolution programming approach on multiple behaviors for the design of application specific programmable processors. ED&TC 1996: 144-150 - [c43]Michael J. Knieser, Christos A. Papachristou:
COMET: a hardware-software codesign methodology. EURO-DAC 1996: 178-183 - [c42]Christos A. Papachristou, Mehrdad Nourani:
False path exclusion in delay analysis of RTL-based datapath-controller designs. EURO-DAC 1996: 336-341 - [c41]Wei Zhao, Christos A. Papachristou:
Synthesis of reusable DSP cores based on multiple behaviors. ICCAD 1996: 103-108 - [c40]J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw! VTS 1996: 506-507 - 1995
- [j10]Wen-Ben Jone, Christos A. Papachristou:
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 374-384 (1995) - [c39]Joan Carletta, Christos A. Papachristou
A method for testability analysis and BIST insertion at the RTL. ED&TC 1995: 600 - [c38]Wei Zhao, Christos A. Papachristou:
Architectural partitioning of control memory for application specific programmable processors. ICCAD 1995: 521-526 - [c37]Joan Carletta, Christos A. Papachristou:
Testability analysis and insertion for RTL circuits based on pseudorandom BIST. ICCD 1995: 162-167 - [c36]Christos A. Papachristou, Mark Spining, Mehrdad Nourani:
A multiple clocking scheme for low power RTL design. ISLPD 1995: 27-32 - [c35]Christos A. Papachristou, Joan Carletta:
Test Synthesis in the Behavioral Domain. ITC 1995: 693-702 - [c34]Joan Carletta, Christos A. Papachristou:
Structural constraints for circular self-test paths. VTS 1995: 486-491 - 1994
- [c33]Joan Carletta, Christos A. Papachristou:
Structural constraints for circular self-test paths. VTS 1994: 87-92 - 1993
- [j9]Christos A. Papachristou
Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing. IEEE Trans. Computers 42(1): 45-61 (1993) - [c32]Mehrdad Nourani, Christos A. Papachristou:
A Layout Estimation Algorithm for RTL Datapaths. DAC 1993: 285-291 - [c31]Christos A. Papachristou
An Approach for Redesigning in Data Path Synthesis. DAC 1993: 419-423 - [c30]Haidar Harmanani, Christos A. Papachristou:
An improved method for RTL synthesis with testability tradeoffs. ICCAD 1993: 30-35 - [c29]Scott Chiu, Christos A. Papachristou:
A Partial Scan Cost Estimation Method at the System Level. ICCD 1993: 146-150 - [c28]H. Fatih Ugurdag, Christos A. Papachristou:
A VLIW architecture based on shifting register files. MICRO 1993: 263-268 - 1992
- [j8]Cris Koutsougeras, George Georgiou, Christos A. Papachristou:
A Feedforward Neural Network Classifier Model: Multiple Classes, Confidence Output Values, and Implementation. Int. J. Pattern Recognit. Artif. Intell. 6(4): 539-569 (1992) - [c27]Mehrdad Nourani, Christos A. Papachristou:
Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. DAC 1992: 99-105 - [c26]Mehrdad Nourani, Christos A. Papachristou, Yoshiyasu Takefuji
A neural network based algorithm for the scheduling problem in high-level synthesis. EURO-DAC 1992: 341-346 - [c25]Haidar Harmanani, Christos A. Papachristou, Scott Chiu, Mehrdad Nourani:
SYNTEST: an environment for system-level design for test. EURO-DAC 1992: 402-407 - [c24]H. Fatih Ugurdag, Christos A. Papachristou:
ALMP: A Shifting Memory Architecture for Loop Pipelining. ICCD 1992: 564-568 - [c23]Michael J. Knieser, Christos A. Papachristou:
Y-Pipe: a conditional branching scheme without pipeline delays. MICRO 1992: 125-128 - 1991
- [j7]Christos A. Papachristou
Microcontrol architectures with sequencing firmware and modular microcode development tools. Microprocessing and Microprogramming 29(5): 303-328 (1991) - [c22]Scott Chiu, Christos A. Papachristou
A Design for Testability Scheme with Applications to Data Path Synthesis. DAC 1991: 271-277 - [c21]Christos A. Papachristou
A Data Path Synthesis Method for Self-Testable Designs. DAC 1991: 378-384 - [c20]Scott Chiu, Christos A. Papachristou:
A Built-In Self-Testing Approach for Minimizing Hardware Overhead. ICCD 1991: 282-285 - [c19]Christos A. Papachristou, Scott Chiu, Haidar Harmanani:
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability. ICCD 1991: 458-462 - 1990
- [j6]Christos A. Papachristou
A design scheme for PLA-based control tables with reduced area and time-delay cost. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 453-472 (1990) - [c18]Christos A. Papachristou
A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. DAC 1990: 77-83 - [c17]Cris Koutsougeras, George Georgiou, Christos A. Papachristou:
Extending Athena: multiple classes and confidence output values. TAI 1990: 712-716 - [c16]Jong-Jiann Shieh, Christos A. Papachristou:
An instruction reoderer for pipelined computers. MICRO 1990: 135-142 - [c15]Djahida Smati, Jerry P.-C. Hwang, Christos A. Papachristou:
SMDSS - a structured microcode development and simulation system. MICRO 1990: 252-259 - [e1]Christos A. Papachristou, Vicki H. Allan:
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990. ACM/IEEE 1990, ISBN 0-89791-413-9 [contents]
1980 – 1989
- 1989
- [c14]Wen-Ben Jone, Christos A. Papachristou:
A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. DAC 1989: 525-534 - [c13]Wen-Ben Jone, Christos A. Papachristou, M. Pereira:
A Scheme for Overlaying Concurrent Testing of VLSI Circuits. DAC 1989: 531-536 - [c12]Jong-Jiann Shieh, Christos A. Papachristou
On reordering instruction streams for pipelined computers. MICRO 1989: 199-206 - 1988
- [c11]Cris Koutsougeras, Christos A. Papachristou
Training of a neural network for pattern classification based on an entropy measure. ICNN 1988: 247-254 - [c10]L. Shih, Christos A. Papachristou:
Mapping of micro data flow computations on parallel microarchitectures. MICRO 1988: 70-72 - 1987
- [j5]Christos A. Papachristou
Associative table lookup processing for multioperand residue arithmetic. J. ACM 34(2): 376-396 (1987) - [c9]Christos A. Papachristou
A Systolic Array Structure for Matrix Multiplication in the Residue Number System. ICS 1987: 716-731 - 1986
- [c8]Christos A. Papachristou
Expert system approach to VLSI cell design (abstract). ACM Conference on Computer Science 1986: 485 - [c7]Cris Koutsougeras, Christos A. Papachristou
Data flow graph partitioning to reduce communication cost. MICRO 1986: 82-91 - 1985
- [j4]Christos A. Papachristou
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories. IEEE Trans. Computers 34(2): 110-116 (1985) - [c6]Christos A. Papachristou
Multi - Input residue arithmetic utilizing read - Only associative memory. IEEE Symposium on Computer Arithmetic 1985: 182-188 - [c5]Jerry P.-C. Hwang, Christos A. Papachristou
Microcode development for microprogrammed processors. MICRO 1985: 145-156 - 1984
- [c4]Christos A. Papachristou, Venkata R. Immaneni, D. B. Sarma:
An automatic migration scheme based on modular microcode and structured firmware sequencing. MICRO 1984: 155-164 - 1983
- [j3]Christos A. Papachristou
Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach. IEEE Trans. Computers 32(10): 961-968 (1983) - 1982
- [c3]Christos A. Papachristou, Satnam Sing Gambhir:
A microsequencer architecture with firmware support for modular microprogramming. MICRO 1982: 105-113 - 1981
- [c2]Christos A. Papachristou
Algorithms for parallel addition and parallel polynomial evaluation. IEEE Symposium on Computer Arithmetic 1981: 256-263 - [c1]Christos A. Papachristou:
Hardware microcontrol schemes using PLAs. MICRO 1981: 3-16
1970 – 1979
- 1978
- [j2]Christos A. Papachristou
An Algorithm for Optimal NAND Cascade Logic Synthesis. IEEE Trans. Computers 27(12): 1099-1111 (1978) - 1977
- [j1]Christos A. Papachristou
Characteristic measures of switching functions. Inf. Sci. 13(1): 51-75 (1977)
Coauthor Index
[i4] [i3] [c126] [c125] [c124] [j24] [c123] [c122] [c121] [c120] [j22] [c118] [c117] [c114] [j21] [c113] [c112] [c111] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [c96] [i2] [i1] [c94] [c92] [c90] [c87] [c86] [j20] [c84] [c83] [c82] [c81] [c80] [c77] [c76] [c75] [c72] [c71] [c70] [c62]
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