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Charlie Hwang
2010 – 2019
- 2011
- [j2]John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits 46(1): 64-75 (2011) - [c2]Hongwei Hong, Zheng Li, Qin Li, Ruizhe Wang, Charlie Hwang:
A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth. ASICON 2011: 315-318 - 2010
- [c1]John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. ISSCC 2010: 342-343
2000 – 2009
- 2007
- [j1]Brian W. Curran, Eric Fluhr, Jose Paredes, Leon J. Sigal, Joshua Friedrich, Yiu-Hing Chan, Charlie Hwang:
Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. IBM J. Res. Dev. 51(6): 715-732 (2007)
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