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Sven-Ole Voigt
2010 – 2019
- 2014
- [j4]Daniel Kliem, Sven-Ole Voigt:
Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning. Microprocess. Microsystems 38(8): 845-859 (2014) - 2013
- [j3]Malte Baesler, Sven-Ole Voigt:
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs. Int. J. Reconfigurable Comput. 2013: 453173:1-453173:16 (2013) - [c7]Daniel Kliem, Sven-Ole Voigt:
An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs. FPL 2013: 1-4 - 2012
- [c6]Daniel Kliem, Sven-Ole Voigt:
A multi-core FPGA-based SoC architecture with domain segregation. ReConFig 2012: 1-7 - 2011
- [c5]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers. ReConFig 2011: 13-19 - 2010
- [j2]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA. Int. J. Reconfigurable Comput. 2010: 357839:1-357839:13 (2010) - [j1]Sven-Ole Voigt, Malte Baesler, Thomas Teufel:
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing. J. Syst. Archit. 56(11): 561-576 (2010) - [c4]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier. FPL 2010: 489-495 - [c3]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
A radix-10 digit recurrence division unit with a constant digit selection function. ICCD 2010: 241-246
2000 – 2009
- 2008
- [b1]Sven-Ole Voigt:
Dynamically reconfigurable dataflow architecture for high performance digital signal processing on multi FPGA platforms. Hamburg University of Technology, 2008, ISBN 978-3-8322-7805-2, pp. 1-112 - [c2]Sven-Ole Voigt, Thomas Teufel:
Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms. FCCM 2008: 261-262 - 2007
- [c1]Sven-Ole Voigt, Thomas Teufel:
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms. FPL 2007: 633-637
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