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Alejandro F. González
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2000 – 2009
- 2005
- [c7]Gilberto A. Gutiérrez
, Gonzalo Navarro, M. Andrea Rodríguez
A spatio-temporal access method based on snapshots and events. GIS 2005: 115-124 - 2003
- [c6]Alejandro F. González, Pinaki Mazumder:
Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes. VLSI Design 2003: 493-492 - 2001
- [j3]Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. IEEE J. Solid State Circuits 36(6): 924-932 (2001) - [c5]Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González, Pinaki Mazumder:
A 250-MHz, 32-bit quantum MOS correlator prototype. ICECS 2001: 1501-1504 - 2000
- [j2]Alejandro F. González, Pinaki Mazumder:
Redundant arithmetic, algorithms and implementations. Integr. 30(1): 13-53 (2000) - [c4]Mayukh Bhattacharya, Shriram Kulkarni, Alejandro F. González, Pinaki Mazumder:
A prototyping technique for large-scale RTD-CMOS circuits. ISCAS 2000: 635-638 - [c3]Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. ISMVL 2000: 323-330
1990 – 1999
- 1998
- [j1]Alejandro F. González, Pinaki Mazumder:
Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices. IEEE Trans. Computers 47(9): 947-959 (1998) - [c2]Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González:
Circuit Design using Resonant Tunneling Diodes. VLSI Design 1998: 501-506 - 1997
- [c1]Alejandro F. González, Pinaki Mazumder:
Compact Signed-Digit Adder Using Multiple-Valued Logic. ARVLSI 1997: 96-113
Coauthor Index
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