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Naoki Fujieda
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2020 – today
- 2023
- [j9]Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe:
Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator. IEICE Trans. Inf. Syst. 106(12): 1940-1950 (2023) - [c16]Naoki Fujieda, Atsuki Okuchi:
A Novel Remote FPGA Lab Platform Using MCU-based Controller Board. TALE 2023: 1-6 - 2022
- [c15]Ryusei Oya, Naoki Fujieda
, Shuichi Ichikawa:
An HLS implementation of on-the-fly randomness test for TRNGs. CANDAR 2022: 151-157 - 2021
- [j8]Shunsuke Matsuoka, Shuichi Ichikawa
A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC). Int. J. Circuit Theory Appl. 49(10): 3354-3367 (2021) - [j7]Naoki Fujieda, Sogo Takashima:
An MMCM-based high-speed true random number generator for Xilinx FPGA. Int. J. Netw. Comput. 11(2): 154-171 (2021) - [c14]Naoki Fujieda
A Python-based evaluation framework for stochastic computing circuits on FPGA SoC. CANDAR (Workshops) 2021: 81-86 - 2020
- [j6]Naoki Fujieda
An Analysis of DCM-Based True Random Number Generator. IEEE Trans. Circuits Syst. II Express Briefs 67-II(6): 1109-1113 (2020) - [c13]Naoki Fujieda
On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs. FPL 2020: 103-108 - [c12]Naoki Fujieda
Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator. CANDAR (Workshops) 2020: 197-203
2010 – 2019
- 2019
- [c11]Naoki Fujieda
A light-weight implementation of latch-based true random number generator. IWCMC 2019: 901-906 - 2018
- [j5]Naoki Fujieda
A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs. IEICE Electron. Express 15(10): 20180386 (2018) - [j4]Naoki Fujieda
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files. IEICE Trans. Inf. Syst. 101-D(6): 1521-1531 (2018) - [c10]Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa:
An Analysis on Randomness of Path ORAM for Light-Weight Implementation. CANDAR Workshops 2018: 163-165 - [c9]Naoki Fujieda
A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity. TENCON 2018: 1489-1492 - 2017
- [j3]Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa:
A Virtual Cache for Overlapped Memory Accesses of Path ORAM. Int. J. Netw. Comput. 7(2): 106-123 (2017) - [c8]Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa:
An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis. CANDAR 2017: 323-325 - [c7]Naoki Fujieda
Evaluation of the hardwired sequence control system generated by high-level synthesis. ISIE 2017: 1261-1267 - 2016
- [j2]Naoki Fujieda
Design and implementation of instruction indirection for embedded software obfuscation. Microprocess. Microsystems 45: 115-128 (2016) - [c6]Naoki Fujieda
Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM. CANDAR 2016: 347-353 - 2015
- [c5]Naoki Fujieda
A Complement to Enhanced Instruction Register File against Embedded Software Falsification. PPREW@ACSAC 2015: 3:1-3:7 - 2013
- [c4]Naoki Fujieda, Shuichi Ichikawa:
An XOR-Based Approach to Merging Entries for Instruction Register Files. CANDAR 2013: 332-337 - 2012
- [c3]Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise:
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. ARC 2012: 138-150 - 2011
- [c2]Naoki Fujieda, Kenji Kise:
A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors. ICNC 2011: 160-165 - [c1]Mochamad Asri, Naoki Fujieda, Kenji Kise:
Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. ISOCC 2011: 207-210
2000 – 2009
- 2009
- [j1]Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise:
SimCell: A Processor Simulator for Multi-Core Architecture Research. Inf. Media Technol. 4(2): 270-281 (2009)
Coauthor Index
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