CMOS Combinational Circuit Sizing by Stage-wise Tapering.

Satyamurthy Pullela Satyamurthy Pullela Rajendran Panda Abhijit Dharchoudhury Gopal Vija CMOS Combinational Circuit Sizing by Stage-wise Tapering. 985-986 1998 conf/date/1998 DATE https://doi.org/10.1109/DATE.1998.656001 https://doi.ieeecomputersociety.org/10.1109/DATE.1998.656001 http://dl.acm.org/citation.cfm?id=368569 db/conf/date/date1998.html#PullelaPDV98

Satyamurthy Pullela Noel Menezes Lawrence T. Pileggi Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. 210-215 1997 16 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/43.573836 db/journals/tcad/tcad16.html#PullelaMP97

Shantanu Ganguly Daksh Lehther Satyamurthy Pullela Clock Distribution Methodology for PowerPC<sup>TM</sup> Microprocessors. 181-189 1997 16 J. VLSI Signal Process. 2-3 https://doi.org/10.1023/A:1007991007969 db/journals/vlsisp/vlsisp16.html#GangulyLP97

Sergey Gavrilov Alexey Glebov Satyamurthy Pullela S. C. Moore Abhijit Dharchoudhury Rajendran Panda Gopalakrishnan Vijayan David T. Blaauw Library-less synthesis for static CMOS combinational logic circuits. 658-662 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643608 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643608 https://dl.acm.org/citation.cfm?id=266570 db/conf/iccad/iccad1997.html#GavrilovGPMDPVB97 Abhijit Dharchoudhury David T. Blaauw Joe Norton Satyamurthy Pullela J. Dunning Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. 143-148 1997 conf/iccd/1997 ICCD db/conf/iccd/iccd97.html#DharchoudhuryBNPD97 https://doi.org/10.1109/ICCD.1997.628861 https://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628861

Satyamurthy Pullela Noel Menezes Lawrence T. Pileggi Post-processing of clock trees via wiresizing and buffering for robust design. 691-701 1996 15 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/43.503938 db/journals/tcad/tcad15.html#PullelaMP96

Noel Menezes Satyamurthy Pullela Lawrence T. Pileggi Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. 690-695 1995 conf/dac/1995 DAC https://doi.org/10.1145/217474.217612 db/conf/dac/dac95.html#MenezesPP95

Jessica Qian Satyamurthy Pullela Lawrence T. Pillage Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. 1526-1535 1994 13 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/43.331409 db/journals/tcad/tcad13.html#QianPP94

Noel Menezes Satyamurthy Pullela Florentin Dartu Lawrence T. Pillage RC interconnect synthesis-a moment fitting approach. 418-425 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629837 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629837 https://dl.acm.org/citation.cfm?id=191506 db/conf/iccad/iccad1994.html#MenezesPDP94 Satyamurthy Pullela Noel Menezes Lawrence T. Pillage Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. 165-170 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164653 db/conf/dac/dac93.html#PullelaMP93 David T. Blaauw Florentin Dartu Abhijit Dharchoudhury J. Dunning Shantanu Ganguly Sergey Gavrilov Alexey Glebov Daksh Lehther Noel Menezes S. C. Moore Joe Norton Rajendran Panda Lawrence T. PileggiLawrence T. Pillage Jessica Qian Gopal Vija Gopalakrishnan Vijayan