A 1.4 pJ/bit, Power-Scalable 16 exttimes12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology - Timothy O. Dickson; Yong Liu; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

A 28 GHz Hybrid PLL in 32 nm SOI CMOS - Mark A. Ferriss; Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Daniel J. Friedman (IEEE J. Solid State Circuits, 2014)

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li; Lawrence T. Pileggi; Arun Natarajan; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 1.4-pJ/b, power-scalable 16 exttimes12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology - Timothy O. Dickson; Yong Liu; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014, 2014)

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan; Alexander V. Rylyakov; Benjamin D. Parker; José A. Tierno; Aydin Babakhani; Soner Yaldiz; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2013)

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing - Bodhisatwa Sadhu; Mark A. Ferriss; Arun Natarajan; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li; Lawrence T. Pileggi; et al. (IEEE J. Solid State Circuits, 2013)

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing" - Bodhisatwa Sadhu; Mark A. Ferriss; Arun S. Natarajan; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li; Lawrence T. Pillage; et al. (IEEE J. Solid State Circuits, 2013)

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability - Charles Lefurgy; Alan J. Drake; Michael S. Floyd; Malcolm Allen-Ware; Bishop Brock; José A. Tierno; John B. Carter; Robert W. Berry (IEEE Micro, 2013)

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Larry T. Pileggi; Ramesh Harjani; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li; Lawrence T. Pileggi; Arun Natarajan; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013, 2013)

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI - Yong Liu; Ping-Hsuan Hsieh; Seongwon Kim; Jae-sun Seo; Robert K. Montoye; Leland Chang; José A. Tierno; Daniel J. Friedman (2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, 2013)

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu; José A. Tierno; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Lawrence T. Pileggi; Ramesh Harjani; et al. (Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012, 2012)

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS - Jean-Olivier Plouchart; Mihai A. T. Sanduleanu; Zeynep Toprak Deniz; Troy J. Beukema; Scott K. Reynolds; Benjamin D. Parker; Michael P. Beakes; José A. Tierno; Daniel J. Friedman (Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012, 2012)

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation - Sameh W. Asaad; Ralph Bellofatto; Bernard Brezzo; Chuck Haymes; Mohit Kapur; Benjamin D. Parker; Thomas Roewer; Proshanta Saha; Todd Takken; José A. Tierno (Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, FPGA 2012, Monterey, California, USA, February 22-24, 2012, 2012)

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu; José A. Tierno; Daniel J. Friedman (2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, 2012)

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan; Alexander V. Rylyakov; Benjamin D. Parker; Aydin Babakhani; Soner Yaldiz; Bodhisatwa Sadhu; Alberto Valdes-Garcia; José A. Tierno; Daniel J. Friedman (Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012, 2012)

Adaptive energy-management features of the IBM POWER7 chip - Michael S. Floyd; Malcolm Allen-Ware; Karthick Rajamani; Tilman Gloekler; Bishop Brock; Pradip Bose; Alper Buyuktosunoglu; Juan C. Rubio; Birgit Schubert; Bruno Spruth; José A. Tierno; Lorena Pesantez (IBM J. Res. Dev., 2011)

Introducing the Adaptive Energy Management Features of the Power7 Chip - Michael S. Floyd; Malcolm Allen-Ware; Karthick Rajamani; Bishop Brock; Charles Lefurgy; Alan J. Drake; Lorena Pesantez; Tilman Gloekler; José A. Tierno; Pradip Bose; Alper Buyuktosunoglu (IEEE Micro, 2011)

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons - Jae-sun Seo; Bernard Brezzo; Yong Liu; Benjamin D. Parker; Steven K. Esser; Robert K. Montoye; Bipin Rajendran; José A. Tierno; Leland Chang; Dharmendra S. Modha; Daniel J. Friedman (2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011, 2011)

Indirect phase noise sensing for self-healing voltage controlled oscillators - Soner Yaldiz; Vehbi Calayir; Xin Li; Lawrence T. Pileggi; Arun Natarajan; Mark A. Ferriss; José A. Tierno (2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011, 2011)

Active management of timing guardband to save energy in POWER7 - Charles Lefurgy; Alan J. Drake; Michael S. Floyd; Malcolm Allen-Ware; Bishop Brock; José A. Tierno; John B. Carter (44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011, 2011)

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz - Montek Singh; José A. Tierno; Alexander V. Rylyakov; Sergey V. Rylov; Steven M. Nowick (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications - Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Jean-Olivier Plouchart; John F. Bulzacchelli; Zeynep Toprak Deniz; Daniel J. Friedman (IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, 2009)

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI - José A. Tierno; Alexander V. Rylyakov; Daniel J. Friedman (IEEE J. Solid State Circuits, 2008)

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI - Alexander V. Rylyakov; José A. Tierno; George English; Michael A. Sperling; Daniel J. Friedman (Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008, 2008)

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS - Alexander V. Rylyakov; José A. Tierno; Didem Zeliha Turker; Jean-Olivier Plouchart; Herschel A. Ainspan; Daniel J. Friedman (2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, 2008)

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI - Alexander V. Rylyakov; José A. Tierno; George English; Daniel J. Friedman; M. Megheli (2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007, 2007)

Integrated transversal equalizers in high-speed fiber-optic systems - Hui Wu; José A. Tierno; Petar K. Pepeljugoski; Jeremy Schaub; Sudhir M. Gowda; Jeffrey A. Kash; Ali Hajimiri (IEEE J. Solid State Circuits, 2003)

An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz - José A. Tierno; Sergey V. Rylov; Alexander V. Rylyakov; Montek Singh; Steven M. Nowick (8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, 2002)

Asynchronous Parallel Prefix Computation - Rajit Manohar; José A. Tierno (IEEE Trans. Computers, 1998)

Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology - Z. John Deng; Steve R. Whiteley; Theodore Van Duzer; José A. Tierno (4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, 1998)

Asynchronous Transpose-Matrix Architectures - José A. Tierno; Prabhakar Kudva (Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, 1997)

The energy and entropy of VLSI computations - José A. Tierno; Rajit Manohar; Alain J. Martin (2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan, 1996)

A 100-MIPS GaAs Asynchronous Microprocessor - José A. Tierno; Alain J. Martin; Drazen Borkovic; Tak-Kwan Lee (IEEE Des. Test Comput., 1994)

Low-energy asynchronous memory design - José A. Tierno; Alain J. Martin (Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994, 1994)