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José A. Tierno
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2010 – 2019
- 2015
- [j16]Timothy O. Dickson, Yong Liu, Sergey V. Rylov
, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50(8): 1917-1931 (2015) - 2014
- [j15]Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman:
A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J. Solid State Circuits 49(4): 1027-1035 (2014) - [j14]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2243-2252 (2014) - [c20]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC 2014: 1-4 - 2013
- [j13]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits 48(4): 996-1008 (2013) - [j12]Bodhisatwa Sadhu
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j11]Bodhisatwa Sadhu
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j10]Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter, Robert W. Berry:
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability. IEEE Micro 33(4): 35-45 (2013) - [j9]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [c19]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC 2013: 1-4 - [c18]Yong Liu, Ping-Hsuan Hsieh
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC 2013: 400-401 - 2012
- [j8]Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman:
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. IEEE J. Solid State Circuits 47(12): 3220-3231 (2012) - [c17]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4 - [c16]Jean-Olivier Plouchart, Mihai A. T. Sanduleanu
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. CICC 2012: 1-4 - [c15]Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno:
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. FPGA 2012: 153-162 - [c14]Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman:
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. ISSCC 2012: 134-136 - [c13]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177 - 2011
- [j7]Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, Juan C. Rubio, Birgit Schubert, Bruno Spruth, José A. Tierno, Lorena Pesantez:
Adaptive energy-management features of the IBM POWER7 chip. IBM J. Res. Dev. 55(3): 8 (2011) - [j6]Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu:
Introducing the Adaptive Energy Management Features of the Power7 Chip. IEEE Micro 31(2): 60-75 (2011) - [c12]Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC 2011: 1-4 - [c11]Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno:
Indirect phase noise sensing for self-healing voltage controlled oscillators. CICC 2011: 1-4 - [c10]Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter:
Active management of timing guardband to save energy in POWER7. MICRO 2011: 1-11 - 2010
- [j5]Montek Singh, José A. Tierno, Alexander V. Rylyakov, Sergey V. Rylov
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1043-1056 (2010)
2000 – 2009
- 2009
- [c9]Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman:
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC 2009: 94-95 - 2008
- [j4]José A. Tierno, Alexander V. Rylyakov, Daniel J. Friedman:
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. IEEE J. Solid State Circuits 43(1): 42-51 (2008) - [c8]Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman:
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. CICC 2008: 431-434 - [c7]Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman:
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC 2008: 516-517 - 2007
- [c6]Alexander V. Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli:
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. ISSCC 2007: 172-173 - 2003
- [j3]Hui Wu, José A. Tierno, Petar K. Pepeljugoski, Jeremy Schaub, Sudhir M. Gowda, Jeffrey A. Kash, Ali Hajimiri
Integrated transversal equalizers in high-speed fiber-optic systems. IEEE J. Solid State Circuits 38(12): 2131-2137 (2003) - 2002
- [c5]José A. Tierno, Sergey V. Rylov, Alexander V. Rylyakov, Montek Singh, Steven M. Nowick:
An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. ASYNC 2002: 84-95
1990 – 1999
- 1998
- [j2]Rajit Manohar, José A. Tierno:
Asynchronous Parallel Prefix Computation. IEEE Trans. Computers 47(11): 1244-1252 (1998) - [c4]Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno:
Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology. ASYNC 1998: 274- - 1997
- [c3]José A. Tierno, Prabhakar Kudva:
Asynchronous Transpose-Matrix Architectures. ICCD 1997: 423-428 - 1996
- [c2]José A. Tierno, Rajit Manohar, Alain J. Martin:
The energy and entropy of VLSI computations. ASYNC 1996: 188-196 - 1994
- [j1]José A. Tierno, Alain J. Martin, Drazen Borkovic, Tak-Kwan Lee:
A 100-MIPS GaAs Asynchronous Microprocessor. IEEE Des. Test Comput. 11(2): 43-49 (1994) - [c1]José A. Tierno, Alain J. Martin:
Low-energy asynchronous memory design. ASYNC 1994: 176-185
Coauthor Index
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