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Frank Hannig
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- affiliation: University of Erlangen-Nuremberg, Germany
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2020 – today
- 2024
- [j40]Christian Heidorn, Muhammad Sabih
, Nicolai Meyerhöfer, Christian Schinabeck
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. Int. J. Parallel Program. 52(1-2): 40-58 (2024) - [c142]Patrick Plagwitz
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC 2024: 3-18 - [c141]Dominik Walter, Thomas Adamtschuk, Frank Hannig, Jürgen Teich:
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. ASAP 2024: 97-106 - [c140]Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich:
Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. DATE 2024: 1-2 - [c139]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
DSL-Based SNN Accelerator Design Using Chisel. DSD 2024: 176-184 - [c138]Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS 2024: 1-5 - [c137]Christian Heidorn, Frank Hannig, Dominik Riedelbauch
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. VEHITS 2024: 64-75 - [i17]Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich:
OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. CoRR abs/2404.15833 (2024) - [i16]Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich:
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. CoRR abs/2407.10734 (2024) - 2023
- [c136]Muhammad Sabih
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys 2023: 87-93 - [i15]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR abs/2306.12742 (2023) - 2022
- [j39]Samer Alhaddad, Jens Förstner, Stefan Groth
The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. 34(14) (2022) - [j38]Marcel Brand
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2661-2666 (2022) - [j37]Frank Hannig, Steven Derrien:
Special Issue on Applied Reconfigurable Computing. J. Signal Process. Syst. 94(9): 847-848 (2022) - [c135]Muhammad Sabih, Frank Hannig, Jürgen Teich:
DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys 2022: 109-115 - [c134]Patrick Plagwitz, Frank Hannig, Jürgen Teich:
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL 2022: 17-23 - [c133]Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich:
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC 2022: 1-8 - [c132]Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich:
Hardware-Aware Evolutionary Filter Pruning. SAMOS 2022: 283-299 - 2021
- [j36]Frank Hannig
Open Source Hardware. Computer 54(10): 111-115 (2021) - [j35]Marcel Brand
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021) - [j34]M. Akif Özkan
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18(3): 765-777 (2021) - [j33]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20(5): 49:1-49:31 (2021) - [j32]Frank Hannig, Dirk Koch:
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. 93(12): 1363-1364 (2021) - [c131]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops 2021: 166-174 - [c130]Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM 2021: 10-19 - [c129]Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL 2021: 388 - [c128]Bo Qiao, Jürgen Teich, Frank Hannig:
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops 2021: 387-396 - [c127]Stefan Groth, Jürgen Teich, Frank Hannig:
Efficient Application of Tensor Core Units for Convolving Images. SCOPES 2021: 1-6 - [e5]Steven Derrien
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings. Lecture Notes in Computer Science 12700, Springer 2021, ISBN 978-3-030-79024-0 [contents] - [i14]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR abs/2101.04395 (2021) - [i13]Frank Hannig, Paolo Meloni, Matteo Spallanzani, Matthias Ziegler:
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). CoRR abs/2102.00818 (2021) - 2020
- [j31]Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann
A bibliometric approach for detecting the gender gap in computer science. Commun. ACM 63(5): 74-80 (2020) - [j30]M. Akif Özkan
AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3202-3214 (2020) - [c126]Dirk Koch, Frank Hannig, Javier Navaridas:
Message from the Conference Chairs - ASAP 2020. ASAP 2020: i-ii - [c125]Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig
A runtime system for finite element methods in a partitioned global address space. CF 2020: 39-48 - [c124]Bo Qiao, M. Akif Özkan
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC 2020: 1-6 - [c123]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops 2020: 185-196 - [c122]Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig
Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP 2020: 11-20 - [c121]Christian Heidorn, Frank Hannig
Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES 2020: 26-31 - [c120]Bo Qiao, Oliver Reiche, M. Akif Özkan
Efficient parallel reduction on GPUs with Hipacc. SCOPES 2020: 58-61 - [c119]Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT 2020: 1-6 - [p6]Christian Lengauer, Sven Apel, Matthias Bolten
ExaStencils: Advanced Multigrid Solver Generation. Software for Exascale Computing 2020: 405-452 - [i12]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig
AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR abs/2002.05796 (2020) - [i11]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR abs/2008.09072 (2020) - [i10]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR abs/2008.11476 (2020)
2010 – 2019
- 2019
- [b3]Sascha Roloff, Frank Hannig, Jürgen Teich:
Modeling and Simulation of Invasive Applications and Architectures. Computer Architecture and Design Methodologies, Springer 2019, ISBN 978-981-13-8386-1, pp. i-xv, 1-168 - [j29]Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. 14(8): 541-556 (2019) - [j28]Richard Membarth
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. 5: 1-20 (2019) - [c118]Jörg Fickenscher
DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. ARCS 2019: 71-86 - [c117]Marcel Brand, Michael Witterauf, Frank Hannig
Anytime instructions for programmable accuracy floating-point arithmetic. CF 2019: 215-219 - [c116]Bo Qiao, Oliver Reiche, Frank Hannig
From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. CGO 2019: 242-253 - [c115]Michael Witterauf, Frank Hannig
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE 2019: 8:1-8:10 - [c114]Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig
SYCL Code Generation for Multigrid Methods. SCOPES 2019: 41-44 - [d2]Bo Qiao, Oliver Reiche
From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization. Version 1.0. Zenodo, 2019 [all versions] - [d1]Bo Qiao, Oliver Reiche
From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization. Version 2.0. Zenodo, 2019 [all versions] - 2018
- [b2]Alexandru-Petru Tanase, Frank Hannig
Symbolic Parallelization of Nested Loop Programs. Springer 2018, ISBN 978-3-319-73908-3, pp. I-XII, 1-176 - [j27]Dietmar Fey, Frank Hannig
Special issue on heterogeneous real-time image processing. J. Real Time Image Process. 14(3): 513-515 (2018) - [j26]Christian Schmitt
Automating the Development of High-Performance Multigrid Solvers. Proc. IEEE 106(11): 1969-1984 (2018) - [j25]Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Process. Lett. 28(4): 1850016:1-1850016:21 (2018) - [j24]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17(2): 31:1-31:27 (2018) - [j23]Oliver Reiche
Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. 90(1): 3-27 (2018) - [c113]Ayesha Afzal
Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. ASAP 2018: 1-8 - [c112]Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP 2018: 1-9 - [c111]Jörg Fickenscher, Jens Schlumberger
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. DATE 2018: 443-448 - [c110]Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal
OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. FCCM 2018: 189-196 - [c109]Bo Qiao, Oliver Reiche, Frank Hannig
Automatic Kernel Fusion for Image Processing DSLs. SCOPES 2018: 76-85 - [c108]Jörg Fickenscher, Frank Hannig
Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. VEHITS 2018: 298-306 - 2017
- [j22]Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, Christian Lengauer:
A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. Int. J. Comput. Sci. Eng. 14(2): 150-163 (2017) - [j21]Frank Hannig
Introduction to the special issue on architecture of computing systems. J. Syst. Archit. 77: 1-2 (2017) - [j20]Heba Khdr
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers 66(3): 488-501 (2017) - [j19]Didem Unat
Trends in Data Locality Abstractions for HPC Systems. IEEE Trans. Parallel Distributed Syst. 28(10): 3007-3020 (2017) - [j18]Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. 89(2): 225-242 (2017) - [c107]M. Akif Ozkan
Hardware design and analysis of efficient loop coarsening and border handling for image processing. ASAP 2017: 155-163 - [c106]Marcel Brand, Frank Hannig
Efficiency in ILP processing by using orthogonality. ASAP 2017: 207 - [c105]Sascha Roloff, Frank Hannig
High performance network-on-chip simulation by interval-based timing predictions. ESTIMedia 2017: 2-11 - [c104]Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). ICCAD 2017: 1026-1033 - [c103]Jörg Fickenscher, Sebastian Reinhart, Frank Hannig
Convoy tracking for ADAS on embedded GPUs. Intelligent Vehicles Symposium 2017: 959-965 - [c102]Oliver Reiche
Auto-vectorization for image processing DSLs. LCTES 2017: 21-30 - [c101]Marcel Brand, Frank Hannig
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC 2017: 5-12 - [c100]Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich:
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig 2017: 1-3 - [c99]Éricles Sousa, Alexandru Tanase, Frank Hannig
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig 2017: 1-8 - [c98]Michael Witterauf, Frank Hannig
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP 2017: 9-15 - 2016
- [j17]Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58(6): 297-307 (2016) - [j16]Richard Membarth, Oliver Reiche
HIPAcc: A Domain-Specific Language and Compiler for Image Processing. IEEE Trans. Parallel Distributed Syst. 27(1): 210-224 (2016) - [c97]Michael Witterauf, Alexandru Tanase, Frank Hannig
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP 2016: 58-66 - [c96]M. Akif Ozkan
FPGA-based accelerator design from a domain-specific language. FPL 2016: 1-9 - [c95]Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich:
Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. HLDVT 2016: 70-77 - [c94]Sascha Roloff, Alexander Pöppl
ActorX10: an actor library for X10. X10@PLDI 2016: 24-29 - [c93]Konrad Häublein, Marc Reichenbach
Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS 2016: 211-218 - [p5]Dirk Koch, Daniel Ziener
FPGA Versus Software Programming: Why, When, and How? FPGAs for Software Programmers 2016: 1-21 - [p4]Frank Hannig
A Quick Tour of High-Level Synthesis Solutions for FPGAs. FPGAs for Software Programmers 2016: 49-59 - [p3]Moritz Schmid, Christian Schmitt
Big Data and HPC Acceleration with Vivado HLS. FPGAs for Software Programmers 2016: 115-136 - [p2]Moritz Schmid, Oliver Reiche
HIPAcc. FPGAs for Software Programmers 2016: 205-223 - [p1]Christian Schmitt
Systems of Partial Differential Equations in ExaSlang. Software for Exascale Computing 2016: 47-67 - [e4]Dirk Koch, Frank Hannig
FPGAs for Software Programmers. Springer 2016, ISBN 978-3-319-26406-6 [contents] - [e3]Frank Hannig
Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings. Lecture Notes in Computer Science 9637, Springer 2016, ISBN 978-3-319-30694-0 [contents] - 2015
- [j15]Frank Hannig
Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures. J. Syst. Archit. 61(10): 600 (2015) - [j14]Oliver Reiche
Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. 61(10): 646-658 (2015) - [j13]Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61(10): 668-680 (2015) - [c92]Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS 2015: 1-8 - [c91]Moritz Schmid, Oliver Reiche
Loop coarsening in C-based High-Level Synthesis. ASAP 2015: 166-173 - [c90]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP 2015: 194-201 - [c89]Sascha Roloff, David Schafhauser, Frank Hannig
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. DAC 2015: 44:1-44:6 - [c88]Sascha Roloff, Stefan Wildermann, Frank Hannig
Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia 2015: 1-2 - [c87]Éricles Sousa
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. IESS 2015: 218-229 - [c86]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE 2015: 188-197 - [c85]Éricles Sousa, Frank Hannig
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES 2015: 121-124 - [i9]Frank Hannig, Dietmar Fey, Anton Lokhmotov:
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). CoRR abs/1502.07241 (2015) - [i8]Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig
Automatic Optimization of Hardware Accelerators for Image Processing. CoRR abs/1502.07448 (2015) - [i7]Frank Hannig
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR abs/1508.06320 (2015) - 2014
- [j12]Richard Membarth, Oliver Reiche
Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language. J. Parallel Distributed Comput. 74(12): 3191-3201 (2014) - [j11]Alexander Grebhahn, Sebastian Kuckuk, Christian Schmitt
Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror. Parallel Process. Lett. 24(3) (2014) - [j10]Frank Hannig
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. 13(4s): 133:1-133:29 (2014) - [j9]Srinivas Boppu, Frank Hannig
Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. 77(1-2): 5-29 (2014) - [j8]Jürgen Teich, Alexandru Tanase, Frank Hannig
Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. 77(1-2): 31-59 (2014) - [c84]Deepak Gangadharan
Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. ACSSC 2014: 398-403 - [c83]Sascha Roloff, Frank Hannig, Jürgen Teich:
Towards Actor-oriented Programming on PGAS-based Multicore Architectures. ARCS Workshops 2014: 1-2 - [c82]Moritz Schmid, Alexandru Tanase, Frank Hannig
Domain-specific augmentations for High-Level Synthesis. ASAP 2014: 173-177 - [c81]Oliver Reiche
Code generation from a domain-specific language for C-based HLS of hardware accelerators. CODES+ISSS 2014: 17:1-17:10 - [c80]Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig
Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP 2014: 1-8 - [c79]Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich:
Code generation for embedded heterogeneous architectures on android. DATE 2014: 1-6 - [c78]Éricles Sousa, Deepak Gangadharan
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. DSD 2014: 74-81 - [c77]Christian Lengauer, Sven Apel, Matthias Bolten
ExaStencils: Advanced Stencil-Code Engineering. Euro-Par Workshops (2) 2014: 553-564 - [c76]Moritz Schmid, Nicolas Apelt, Frank Hannig
An image processing library for C-based high-level synthesis. FPL 2014: 1-4 - [c75]Christian Schmitt
An Evaluation of Domain-Specific Language Technologies for Code Generation. ICCSA (Workshops/Short Papers/Posters) 2014: 18-26 - [c74]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE 2014: 219-228 - [c73]Christian Schmitt
ExaSlang: a domain-specific language for highly scalable multigrid solvers. WOLFHPC@SC 2014: 42-51 - [i6]Frank Hannig, Jürgen Teich:
Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). CoRR abs/1405.2281 (2014) - [i5]Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Massively Parallel Processor Architectures for Resource-aware Computing. CoRR abs/1405.2907 (2014) - [i4]Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Ulrich Rüde:
A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms. CoRR abs/1406.5369 (2014) - [i3]Frank Hannig, Dirk Koch, Daniel Ziener:
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). CoRR abs/1408.4423 (2014) - [i2]Moritz Schmid, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich:
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs. CoRR abs/1408.4721 (2014) - 2013
- [c72]Jürgen Teich, Alexandru Tanase, Frank Hannig
Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP 2013: 1-9 - [c71]Srinivas Boppu, Frank Hannig
Loop program mapping and compact code generation for programmable hardware accelerators. ASAP 2013: 10-17 - [c70]Frank Hannig
System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers 2013: 2:1-2:4 - [c69]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP 2013: 88-95 - [c68]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP 2013: 353-354 - [c67]Alexandru Tanase, Vahid Lari, Frank Hannig
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO 2013: 53-62 - [c66]Moritz Schmid, Frank Hannig
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO 2013: 497-506 - [c65]Moritz Schmid, Markus Blocherer, Frank Hannig
Real-timerange image preprocessing on FPGAs. ReConFig 2013: 1-8 - [c64]Sascha Roloff, Andreas Weichslgartner
NoC simulation in heterogeneous architectures for PGAS programming model. M-SCOPES 2013: 77-85 - 2012
- [j7]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig
Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. 18(1): 2:1-2:25 (2012) - [c63]Richard Membarth, Jan-Hugo Lupp, Frank Hannig
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. ARCS 2012: 147-159 - [c62]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig
Design of Low Power On-chip Processor Arrays. ASAP 2012: 165-168 - [c61]Sascha Roloff, Frank Hannig
Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. ASP-DAC 2012: 187-192 - [c60]Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich:
A prototype of an invasive tightly-coupled processor array. DASIP 2012: 1-2 - [c59]Richard Membarth, Frank Hannig
Mastering Software Variant Explosion for GPU Accelerators. Euro-Par Workshops 2012: 123-132 - [c58]Moritz Schmid, Frank Hannig
Power Management Strategies for Serial RapidIO Endpoints in FPGAs. FCCM 2012: 101-108 - [c57]Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, Aurang Zaib:
An integrated simulation framework for invasive computing. FDL 2012: 209-216 - [c56]Richard Membarth, Frank Hannig
Generating Device-specific GPU Code for Local Operators in Medical Imaging. IPDPS 2012: 569-581 - [c55]Richard Membarth, Frank Hannig
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. ISPDC 2012: 211-218 - [c54]Richard Membarth, Frank Hannig
Towards Domain-Specific Computing for Stencil Codes in HPC. SC Companion 2012: 1133-1138 - [c53]Sascha Roloff, Frank Hannig
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation. Map2MPSoC/SCOPES 2012: 52-61 - 2011
- [j6]Dmitrij Kissler, D. Gran, Zoran Salcic
Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. IEEE Embed. Syst. Lett. 3(2): 58-61 (2011) - [j5]Dmitrij Kissler, Frank Hannig
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. 7(1): 29-40 (2011) - [c52]Richard Membarth, Frank Hannig
Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. ARCS 2011: 62-73 - [c51]Vahid Lari, Andriy Narovlyanskyy, Frank Hannig
Decentralized dynamic resource management support for massively parallel processor arrays. ASAP 2011: 87-94 - [c50]Vahid Lari, Frank Hannig
Distributed Resource Reservation in Massively Parallel Processor Arrays. IPDPS Workshops 2011: 318-321 - [c49]Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich:
Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor. MARC Symposium 2011: 111-114 - [c48]Richard Membarth, Frank Hannig
Detector defect correction of medical images on graphics processors. Image Processing 2011: 79624M - [c47]Srinivas Boppu, Frank Hannig
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig 2011: 392-397 - [c46]Richard Membarth, Frank Hannig
Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration. SASP 2011: 78-81 - [c45]Frank Hannig
Resource-aware programming and simulation of MPSoC architectures through extension of X10. SCOPES 2011: 48-55 - [e2]Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca:
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1291-3 [contents] - 2010
- [c44]Hritam Dutta, Frank Hannig
Modeling and synthesis of communication subsystems for loop accelerator pipelines. ASAP 2010: 125-132 - [c43]Tom Vander Aa
Compilation techniques for CGRAs: exploring all parallelization approaches. CODES+ISSS 2010: 185-186 - [c42]Frank Hannig
A deeply pipelined and parallel architecture for denoising medical images. FPT 2010: 485-490 - [e1]François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski:
21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010. IEEE Computer Society 2010, ISBN 978-1-4244-6967-3 [contents]
2000 – 2009
- 2009
- [b1]Frank Hannig:
Scheduling Techniques for High-Throughput Loop Accelerators. University of Erlangen-Nuremberg, 2009, ISBN 978-3-86853-220-3, pp. 1-305 - [j4]Dmitrij Kissler, Andreas Strawetz, Frank Hannig
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electron. 5(1): 96-105 (2009) - [j3]Hritam Dutta, Dmitrij Kissler, Frank Hannig
A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems 33(1): 53-62 (2009) - [c41]Frank Hannig
Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27 - [c40]Hritam Dutta, Frank Hannig
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245 - [c39]Hritam Dutta, Jiali Zhai, Frank Hannig
Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP 2009: 161-168 - [c38]Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP 2009: 211-214 - [c37]Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich:
Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE 2009: 135-140 - [c36]Abdulazim Amouri, Farhadur Arifin, Frank Hannig
FPGA implementation of an invasive computing architecture. FPT 2009: 135-142 - [c35]Vahid Lari, Frank Hannig
System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. ICPP Workshops 2009: 528-534 - [c34]Richard Membarth, Frank Hannig
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS 2009: 277-288 - 2008
- [c33]Frank Hannig
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289 - [c32]Christophe Wolinski, Krzysztof Kuchcinski
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD 2008: 345-352 - [c31]Rainer Schaffer, Renate Merker, Frank Hannig
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398 - [c30]Christophe Wolinski, Krzysztof Kuchcinski
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309 - [c29]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig
Coarse-grained reconfiguration. FPL 2008: 349 - [c28]Christophe Wolinski, Krzysztof Kuchcinski
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396 - [c27]Frank Hannig, Holger Ruckdeschel, Jürgen Teich:
The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. MBMV 2008: 129-138 - [c26]Dmitrij Kissler, Andreas Strawetz, Frank Hannig
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317 - 2007
- [j2]Hritam Dutta, Frank Hannig
Efficient control generation for mapping nested loop programs onto processor arrays. J. Syst. Archit. 53(5-6): 300-309 (2007) - [c25]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282 - [c24]Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24 - [c23]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - [c22]Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig
Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80 - 2006
- [j1]Frank Hannig, Hritam Dutta, Jürgen Teich:
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. Int. J. Embed. Syst. 2(1/2): 114-127 (2006) - [c21]Hritam Dutta, Frank Hannig
Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190 - [c20]Hritam Dutta, Frank Hannig
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340 - [c19]Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195 - [c18]Dmitrij Kissler, Frank Hannig
A highly parameterizable parallel processor array architecture. FPT 2006: 105-112 - [c17]Dmitrij Kissler, Frank Hannig
Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC 2006: 1-4 - [c16]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker:
An Architecture Description Language for Massively Parallel Processor Architectures. MBMV 2006: 11-20 - [c15]Hritam Dutta, Frank Hannig
Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160 - [c14]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37 - 2005
- [c13]Thomas Schlichter, Christian Haubelt
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP 2005: 9-14 - [c12]Frank Hannig, Jürgen Teich:
Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84 - [c11]Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104 - [c10]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34 - [c9]Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich:
Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61 - [i1]Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device. CoRR abs/cs/0505005 (2005) - 2004
- [c8]Frank Hannig, Jürgen Teich:
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP 2004: 17-27 - [c7]Frank Hannig, Hritam Dutta, Jürgen Teich:
Regular mapping for coarse-grained reconfigurable architectures. ICASSP (5) 2004: 57-60 - [c6]Frank Hannig, Hritam Dutta, Jürgen Teich:
Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004 - [c5]Frank Hannig, Jürgen Teich:
Dynamic Piecewise Linear/Regular Algorithms. PARELEC 2004: 79-84 - [c4]Alexey Kupriyanov, Frank Hannig, Jürgen Teich:
High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529 - 2002
- [c3]Marcus Bednara, Frank Hannig
Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170 - [c2]Frank Hannig, Jürgen Teich:
Energy estimation of nested loop programs. SPAA 2002: 149-150 - 2001
- [c1]Frank Hannig
Design Space Exploration for Massively Parallel Processor Arrays. PaCT 2001: 51-65
Coauthor Index
M. Akif Özkan
aka: M. Akif Ozkan
aka: M. Akif Ozkan
Éricles Sousa
aka: Éricles Rodrigues Sousa
aka: Éricles Rodrigues Sousa
Alexandru Tanase
aka: Alexandru-Petru Tanase
aka: Alexandru-Petru Tanase
[j40] [c142] [c141] [c140] [c139] [c138] [c137] [i17] [i16] [c136] [i15] [j39] [j38] [c135] [c134] [c133] [c132] [j36] [j35] [j34] [j33] [c131] [c130] [c129] [c128] [c127] [i14] [j31] [j30] [c125] [c124] [c123] [c122] [c121] [c120] [c119] [p6] [i12] [i11] [i10] [b3] [j29] [j28] [c118] [c117] [c116] [c115] [c114] [d2] [d1] [b2] [j26] [j25] [j24] [j23] [c113] [c112] [c111] [c109] [c108] [j22] [j20] [j18] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [j16] [c97] [c96] [c95] [c94] [c93] [p2] [p1] [e3] [j14] [j13] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [i8] [j12] [j11] [j9] [j8] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [i6] [i5] [i4] [i2] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [j7] [c63] [c62] [c61] [c60] [c59] [c58] [c56] [c55] [c54] [c53] [j6] [j5] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c42] [e1] [j4] [j3] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [j2] [c25] [c24] [c23] [c22] [j1] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [i1] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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