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Juan Valverde
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2010 – 2019
- 2019
- [c8]Alejandro G. Gener, Juan Valverde, J. Andrés Otero, Philip J. Harris:
A Fast Prototyping Workflow for Reconfigurable SDR Applications. ReCoSoC 2019: 66-73 - 2018
- [j3]Alfonso Rodríguez
, Juan Valverde, Jorge Portilla
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. Sensors 18(6): 1877 (2018) - 2015
- [c7]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. ISCAS 2015: 1902 - [c6]Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre:
Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. ReConFig 2015: 1-7 - [c5]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Execution modeling in self-aware FPGA-based architectures for efficient resource management. ReCoSoC 2015: 1-8 - 2014
- [c4]Blanca López, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Power-aware multi-objective evolvable hardware system on an FPGA. AHS 2014: 61-68 - [c3]Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL 2014: 1-4 - [c2]Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. ReCoSoC 2014: 1-7 - 2012
- [j2]Juan Valverde, Victor Rosello, Gabriel Mujica
Wireless Sensor Network for Environmental Monitoring: Application in a Coffee Factory. Int. J. Distributed Sens. Networks 8 (2012) - [j1]Juan Valverde, Andrés Otero
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors 12(3): 2667-2692 (2012) - [c1]Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla
Power management techniques in an FPGA-based WSN node for high performance applications. ReCoSoC 2012: 1-8
Coauthor Index
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