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Sudeb Dasgupta
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2020 – today
- 2025
- [j34]Mahipal Dargupally
, Lomash Chandra Acharya
A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime. IEEE Trans. Very Large Scale Integr. Syst. 33(3): 771-779 (2025) - 2024
- [j33]Lomash Chandra Acharya
Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4715-4725 (2024) - [j32]Dinesh Kushwaha
Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3166-3170 (2024) - [c48]Subhradip Chakraborty
An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. AICAS 2024: 184-188 - [c47]Sambhav Sharma, Garima Choudhary, Neha Gupta, Sunil Rathore, Anand Bulusu, Sudeb Dasgupta:
TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM Architectures. APCCAS 2024: 524-528 - [c46]Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS 2024: 1-5 - [c45]Jyoti Patel, Sankalp Rai, Vivek Kumar, Sudeb Dasgupta:
Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application. ISCAS 2024: 1-5 - [c44]Subhradip Chakraborty
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. ISQED 2024: 1-6 - [c43]Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED 2024: 1-8 - [c42]Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu:
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. ISQED 2024: 1-8 - [c41]Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS 2024: 1-5 - [c40]Anmol Singla, Dinesh Kushwaha, Gulyawar Aman, Shubhradin Chakraborty, Abhishek Goel, Anand Bulusu, Sudeb Dasgupta:
An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture. NewCAS 2024: 233-237 - [c39]Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta:
Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. NewCAS 2024: 243-247 - 2023
- [j31]Khoirom Johnson Singh
Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations. Microelectron. J. 142: 105981 (2023) - [j30]Lomash Chandra Acharya
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2657-2663 (2023) - [c38]Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS 2023: 1-5 - [c37]Jyoti Patel, Govind Sharma, Chitraja Rajan, Vivek Kumar
Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET. APCCAS 2023: 90-94 - [c36]Ravi, Lomash Chandra Acharya
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS 2023: 100-104 - [c35]Mahipal Dargupally, Lomash Chandra Acharya
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. APCCAS 2023: 105-109 - [c34]Lomash Chandra Acharya
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD 2023: 1-4 - [c33]Vivek Kumar
FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. VLSID 2023: 1-6 - [c32]Ashutosh Yadav
Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. VLSID 2023: 59-62 - [c31]Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID 2023: 359-364 - 2022
- [j29]Neeraj Mishra
Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4415-4428 (2022) - [j28]Dinesh Kushwaha
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2311-2315 (2022) - [c30]Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu:
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 2022: 1-4 - [c29]Nitanshu Chauhan, Chirag Garg, Kai Ni, Amit Kumar Behera, Sarita Yadav, Shashank Banchhor, Navjeet Bagga
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI. IRPS 2022: 23-1 - [c28]Dinesh Kushwaha, Aditya Sharma
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS 2022: 1556-1560 - [c27]Khoirom Johnson Singh, Lomash Chandra Acharya
Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. ISCAS 2022: 3423-3427 - [c26]Vivek Kumar
FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet. VDAT 2022: 3-11 - [c25]Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan:
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. VDAT 2022: 85-96 - [c24]Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta:
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID 2022: 292-296 - [e3]Ambika Prasad Shah
VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers. Communications in Computer and Information Science 1687, Springer 2022, ISBN 978-3-031-21513-1 [contents] - 2021
- [c23]Ashutosh Yadav
Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm. ICM 2021: 166-169 - [c22]Khoirom Johnson Singh
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. ISCAS 2021: 1-5 - [c21]Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu:
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED 2021: 251-256 - 2020
- [j27]Neeraj Mishra
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals. IEEE Trans. Circuits Syst. 67-II(11): 2352-2356 (2020)
2010 – 2019
- 2019
- [e2]Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma:
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Communications in Computer and Information Science 1066, Springer 2019, ISBN 978-981-32-9766-1 [contents] - 2018
- [j26]Sudip Roy, Brajesh Kumar Kaushik
Selected Articles from VDAT 2017 Conference. J. Low Power Electron. 14(2): 255-256 (2018) - 2017
- [e1]Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh:
VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers. Communications in Computer and Information Science 711, Springer 2017, ISBN 978-981-10-7469-1 [contents] - 2016
- [j25]Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta:
Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. Microelectron. J. 55: 19-25 (2016) - [c20]Archana Pandey
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSID 2016: 288-293 - [c19]Sarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain:
Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases. VLSID 2016: 361-366 - 2015
- [j24]Ashish Joshi, S. K. Manhas, Satinder K. Sharma
An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications. Microelectron. J. 46(6): 453-461 (2015) - [j23]Gaurav Kaushal
Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectron. J. 46(12): 1239-1247 (2015) - [c18]Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand:
Efficient static D-latch standard cell characterization using a novel setup time model. ISQED 2015: 371-378 - [c17]Arvind Kumar Sharma, Neeraj Mishra
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT 2015: 1-6 - [c16]Sudeb Dasgupta, Bulusu Anand:
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges. VLSID 2015: 12-13 - 2014
- [j22]Naushad Alam
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1714-1726 (2014) - [c15]Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta:
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSID 2014: 411-414 - 2013
- [j21]Menka Yadav, Anand Bulusu, Sudeb Dasgupta:
Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. Microelectron. J. 44(12): 1251-1259 (2013) - [j20]Naushad Alam
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices. Microelectron. Reliab. 53(3): 379-385 (2013) - [j19]Naushad Alam
The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design. Microelectron. Reliab. 53(5): 718-724 (2013) - [c14]Surabhi Singh, Brajesh Kumar Kaushik
A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits. VDAT 2013: 146-152 - [c13]Jainender Kumar, Manoj Kumar Majumder
Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations. VDAT 2013: 214-222 - [c12]Pankaj Kumar Pal
Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers. VDAT 2013: 267-273 - 2012
- [j18]Surendra S. Rathod
Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients. IET Circuits Devices Syst. 6(4): 218-226 (2012) - [j17]Surendra S. Rathod
Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity. J. Circuits Syst. Comput. 21(4) (2012) - [j16]Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta:
Impact of dual-k spacer on analog performance of underlap FinFET. Microelectron. J. 43(11): 883-887 (2012) - [c11]Naushad Alam
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues. ISED 2012: 213-215 - [c10]Baljit Kaur
An accurate current source model for CMOS based combinational logic cell. ISQED 2012: 561-565 - [c9]Naushad Alam
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. ISQED 2012: 717-722 - [c8]Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta:
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. VDAT 2012: 46-51 - [c7]Naushad Alam
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance. VDAT 2012: 357-359 - 2011
- [j15]Surendra S. Rathod
Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact. IET Circuits Devices Syst. 5(1): 52-58 (2011) - [j14]Balwinder Raj
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. J. Low Power Electron. 7(2): 163-171 (2011) - [j13]Surendra S. Rathod
Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation. Microelectron. J. 42(1): 165-172 (2011) - [j12]Santosh Kumar Vishvakarma
Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET. Microelectron. J. 42(5): 688-692 (2011) - [j11]Ramesh Vaddi
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options. Microelectron. J. 42(5): 798-807 (2011) - [j10]Surendra S. Rathod
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier. Microelectron. Reliab. 51(4): 773-780 (2011) - [c6]Ramesh Vaddi
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. ISVLSI 2011: 37-42 - [c5]Arnab Kumar Biswas
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. ISVLSI 2011: 108-113 - [c4]Balwinder Raj
Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. SocProS (2) 2011: 365-375 - 2010
- [j9]Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal:
Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic. IET Circuits Devices Syst. 4(6): 548-560 (2010) - [j8]Ramesh Vaddi
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. J. Low Power Electron. 6(1): 103-114 (2010) - [j7]Surendra S. Rathod
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. J. Low Power Electron. 6(4): 533-544 (2010) - [j6]Ramesh Vaddi
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. Microelectron. J. 41(4): 195-211 (2010) - [j5]Surendra S. Rathod
A proposed DG-FinFET based SRAM cell design with RadHard capabilities. Microelectron. Reliab. 50(8): 1181-1188 (2010) - [c3]Balwinder Raj
Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach. EMS 2010: 526-530
2000 – 2009
- 2009
- [j4]Y. K. Sudharshan, D. Sreenu, Ashok K. Saxena, Sudeb Dasgupta:
Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study. J. Low Power Electron. 5(1): 40-49 (2009) - [j3]Ramesh Vaddi
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications. VLSI Design 2009: 283702:1-283702:14 (2009) - [c2]Maruthi Chandrasekhar Bh, Sudeb Dasgupta:
A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications. ISQED 2009: 447-450 - 2008
- [j2]Deblina Sarkar, Deepanjan Datta, Sudeb Dasgupta:
Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design. J. Comput. 3(2): 37-47 (2008) - 2007
- [c1]Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta:
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. VLSI Design 2007: 183-188 - 2006
- [j1]Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta:
Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET. Microelectron. J. 37(6): 537-545 (2006)
Coauthor Index
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