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Abinash Roy
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2020 – today
- 2022
- [j5]Rassul Bairamkulov
, Abinash Roy, Mahalingam Nagarajan, Vaishnav Srinivas
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2263-2275 (2022) - 2021
- [c13]Rassul Bairamkulov
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping. DAC 2021: 283-288 - 2020
- [c12]Rassul Bairamkulov
Graph-Based Power Network Routing for Board-Level High Performance Systems. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c11]Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas
Learning-based prediction of package power delivery network quality. ASP-DAC 2019: 160-166 - 2010
- [j4]Abinash Roy, Jingye Xu, Masud H. Chowdhury:
Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 338-342 (2010)
2000 – 2009
- 2008
- [j3]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Noise separation in analog integrated circuits using independent component analysis technique. Integr. Comput. Aided Eng. 15(2): 163-180 (2008) - [j2]Jingye Xu, Vivek Nigam, Abinash Roy, Masud H. Chowdhury:
Compound noise separation in digital circuits using blind source separation. Microelectron. J. 39(8): 1083-1092 (2008) - [c10]Abinash Roy, Jingye Xu, Masud H. Chowdhury:
Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects. ICECS 2008: 1055-1058 - [c9]Abinash Roy, Masud H. Chowdhury:
Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. ISCAS 2008: 2426-2429 - [c8]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Optimization technique for flip-flop inserted global interconnect. ISCAS 2008: 3386-3389 - 2007
- [j1]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Power Consumption and BER of Flip-Flop Inserted Global Interconnect. VLSI Design 2007: 42829:1-42829:8 (2007) - [c7]Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury:
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. DAC 2007: 184-187 - [c6]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. DATE 2007: 1218-1223 - [c5]Abinash Roy, Sharada Jha, Masud H. Chowdhury:
Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects. ICECS 2007: 705-708 - [c4]Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury:
Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. ISCAS 2007: 621-624 - [c3]Abinash Roy, Masud H. Chowdhury:
Global Interconnect Optimization in the Presence of On-chip Inductance. ISCAS 2007: 885-888 - [c2]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. ISCAS 2007: 3716-3719 - 2006
- [c1]Abinash Roy, Masud H. Chowdhury:
Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect. APCCAS 2006: 1422-1425
Coauthor Index
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