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Richard C. Ruby
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2010 – 2019
- 2019
- [j3]Jabeom Koo, Keping Wang, Richard C. Ruby, Brian P. Otis:
A 2-GHz FBAR-Based Transformer Coupled Oscillator Design With Phase Noise Reduction. IEEE Trans. Circuits Syst. II Express Briefs 66-II(4): 542-546 (2019) - [c7]Bob Wiser, Kannan A. Sankaragomathi, Justin Schauer, Sean Korhummel, Pouya Kavousian, Daniel J. Yeager, Nivi Arumugam, Nate Pletcher, David Barkin, Reed Parker, Lori Callaghan, Richard C. Ruby, Brian Otis:
A 1.53 mm3 crystal-less standards-compliant Bluetooth Low Energy module for volume constrained wireless sensors. VLSI Circuits 2019: 84- - 2018
- [j2]Jabeom Koo, Kannan A. Sankaragomathi, Richard C. Ruby, Brian Otis:
A ± 1.55ppm Stable FBAR Reference Clock with Oven-Controlled Temperature Compensation. J. Electr. Comput. Eng. 2018: 5453432:1-5453432:8 (2018) - [j1]Keping Wang, Lei Qiu, Jabeom Koo, Richard C. Ruby, Brian Otis:
Design of 1.8-mW PLL-Free 2.4-GHz Receiver Utilizing Temperature-Compensated FBAR Resonator. IEEE J. Solid State Circuits 53(6): 1628-1639 (2018) - 2017
- [c6]Jabeom Koo, Keping Wang, Richard C. Ruby, Brian P. Otis:
A 350uW 2GHz FBAR transformer coupled Colpitts oscillator with close-in phase noise reduction. CICC 2017: 1-4 - 2015
- [c5]Manohar Nagaraju, Andrew Lingley, Suresh Sridharan, Jingren Gu, Richard C. Ruby, Brian P. Otis:
27.4 A 0.8mm3 ±0.68psi single-chip wireless pressure sensor for TPMS applications. ISSCC 2015: 1-3 - [c4]Kannan A. Sankaragomathi, Jabeom Koo, Richard C. Ruby, Brian P. Otis:
25.9 A ±3ppm 1.1mW FBAR frequency reference with 750MHz output and 750mV supply. ISSCC 2015: 1-3 - 2014
- [c3]Keping Wang, Jabeom Koo, Richard C. Ruby, Brian P. Otis:
21.7 A 1.8mW PLL-free channelized 2.4GHz ZigBee receiver utilizing fixed-LO temperature-compensated FBAR resonator. ISSCC 2014: 372-373 - 2012
- [c2]Julie R. Hu, Richard C. Ruby, Brian P. Otis:
A 1.5GHz 0.2psRMS jitter 1.5mW divider-less FBAR ADPLL in 65nm CMOS. CICC 2012: 1-4 - 2010
- [c1]Julie R. Hu, Richard C. Ruby, Brian P. Otis:
A 1.56GHz wide-tuning all digital FBAR-based PLL in 0.13µm CMOS. CICC 2010: 1-4
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