default search action
Shouyi Yin
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [j159]Weiwei Wu, Fengbin Tu, Xiangyu Li, Shaojun Wei, Shouyi Yin:
SWG: an architecture for sparse weight gradient computation. Sci. China Inf. Sci. 67(2) (2024) - [j158]Fengbin Tu
, Zihan Wu
MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. IEEE J. Solid State Circuits 59(1): 90-101 (2024) - [j157]Ruiqi Guo
CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering. IEEE J. Solid State Circuits 59(10): 3317-3329 (2024) - [j156]Yubin Qin
Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow. IEEE J. Solid State Circuits 59(10): 3342-3356 (2024) - [c158]Zhou Wang, Haochen Du, Baoyi Han, Yanqing Xu, Xiaonan Tang, Yang Zhou, Zhe Zheng, Wenpeng Cui, Yanwei Xiong, Shaojun Wei, Shushan Qiao, Shouyi Yin:
RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism. AICAS 2024: 297-301 - [c157]Zhou Wang, Haochen Du, Baoyi Han, Yanqing Xu, Xiaonan Tang, Yang Zhou, Zhe Zheng, Wenpeng Cui, Yanwei Xiong, Shaojun Wei, Shushan Qiao, Shouyi Yin:
RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism. AICAS 2024: 302-306 - [c156]Pengyu He, Yuanzhe Zhao, Heng Xie, Yang Wang, Shouyi Yin, Li Li, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang:
A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. CICC 2024: 1-2 - [c155]Dajiang Liu, Yuxin Xia, Jiaxing Shang, Jiang Zhong, Peng Ouyang, Shouyi Yin:
E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping. HPCA 2024: 46-60 - [c154]Zhiheng Yue, Huizheng Wang, Jiahao Fang, Jinyi Deng, Guangyang Lu, Fengbin Tu, Ruiqi Guo, Yuxuan Li, Yubin Qin, Yang Wang, Chao Li, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin:
Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. ISCA 2024: 396-409 - [c153]Yubin Qin, Yang Wang, Zhiren Zhao, Xiaolong Yang, Yang Zhou, Shaojun Wei, Yang Hu, Shouyi Yin:
MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition. ISCA 2024: 1032-1047 - [c152]Zhiheng Yue, Xujiang Xiang
15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. ISSCC 2024: 276-278 - [c151]Ruiqi Guo
20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. ISSCC 2024: 362-364 - [c150]Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin:
34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications. ISSCC 2024: 566-568 - [c149]Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin:
ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. VLSI Technology and Circuits 2024: 1-2 - [c148]Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin:
A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. VLSI Technology and Circuits 2024: 1-2 - [c147]Ruiqi Guo, Xiaofeng Chen, Lei Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin:
A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation. VLSI Technology and Circuits 2024: 1-2 - [c146]Yubin Qin, Yang Wang, Xiaolong Yang, Zhiren Zhao, Shaojun Wei, Yang Hu, Shouyi Yin:
A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication. VLSI Technology and Circuits 2024: 1-2 - [i13]Jinyi Deng, Xinru Tang, Zhiheng Yue, Guangyang Lu, Qize Yang, Jiahao Zhang, Jinxi Li, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin:
Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture. CoRR abs/2405.17221 (2024) - [i12]Jiahao Fang, Huizheng Wang, Qize Yang, Dehao Kong, Xu Dai, Jinyi Deng, Yang Hu, Shouyi Yin:
PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training. CoRR abs/2406.03868 (2024) - [i11]Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qize Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin:
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. CoRR abs/2407.10416 (2024) - 2023
- [j155]Yihong Zhu
RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems. IEEE J. Solid State Circuits 58(1): 124-140 (2023) - [j154]Yang Wang
An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention. IEEE J. Solid State Circuits 58(1): 227-242 (2023) - [j153]Fengbin Tu
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. IEEE J. Solid State Circuits 58(1): 243-255 (2023) - [j152]Ruiqi Guo
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. IEEE J. Solid State Circuits 58(3): 852-866 (2023) - [j151]Fengbin Tu
TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. IEEE J. Solid State Circuits 58(6): 1798-1809 (2023) - [j150]Fengbin Tu
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 109-121 (2023) - [j149]Mingyang Kou
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2552-2565 (2023) - [j148]Xiangyu Kong
M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2938-2951 (2023) - [j147]Yiqi Wang
SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 214-227 (2023) - [j146]Shaojun Wei
Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1228-1241 (2023) - [j145]Weiwei Wu
STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2370-2383 (2023) - [c145]Xiaofeng Chen, Ruiqi Guo, Zhiheng Yue, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin:
A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions. AICAS 2023: 1-5 - [c144]Zhou Wang, Jingchuan Wei, Xiaonan Tang, Boxiao Han, Hongjun He, Leibo Liu, Shaojun Wei, Shouyi Yin:
TPE: A High-Performance Edge-Device Inference with Multi-level Transformational Mechanism. AICAS 2023: 1-5 - [c143]Ruiqi Guo
CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering. A-SSCC 2023: 1-3 - [c142]Yubin Qin, Yang Wang, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Yang Zhou, Yuanqi Fan, Jingchuan Wei, Tianbao Chen, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin:
A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination. A-SSCC 2023: 1-3 - [c141]Dajiang Liu, Di Mou, Rong Zhu, Yan Zhuang, Jiaxing Shang, Jiang Zhong, Shouyi Yin:
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs. DAC 2023: 1-6 - [c140]Zhou Wang, Jingchuan Wei, Boxiao Han, Hongjun He, Leibo Liu, Shaojun Wei, Shouyi Yin:
CPE: An Energy-Efficient Edge-Device Training with Multi-dimensional Compression Mechanism. DAC 2023: 1-6 - [c139]Qidie Wu
RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. DAC 2023: 1-6 - [c138]Yubin Qin
FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction. ISCA 2023: 22:1-22:14 - [c137]Zhiheng Yue, Yang Wang, Huizheng Wang
CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. ISSCC 2023: 138-139 - [c136]Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin:
MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. ISSCC 2023: 248-249 - [c135]Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin:
TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. ISSCC 2023: 254-255 - [c134]Jinyi Deng
Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. MICRO 2023: 1395-1408 - [c133]Yang Wang, Yubin Qin, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin:
A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing. VLSI Technology and Circuits 2023: 1-2 - [i10]Shitong Shao, Xu Dai
Catch-Up Distillation: You Only Need to Train Once for Accelerating Sampling. CoRR abs/2305.10769 (2023) - [i9]Jinyi Deng
Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. CoRR abs/2307.02847 (2023) - [i8]Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin:
WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. CoRR abs/2309.01273 (2023) - [i7]Yang Hu, Xinhan Lin, Huizheng Wang, Zhen He, Xingmao Yu, Jiahao Zhang, Qize Yang, Zheng Xu, Sihan Guan, Jiahao Fang, Haoran Shang, Xinru Tang, Xu Dai
Wafer-scale Computing: Advancements, Challenges, and Future Perspectives. CoRR abs/2310.09568 (2023) - 2022
- [j144]Chenchen Deng, Min Zhu, Jinjiang Yang, Youyu Wu, Jiaji He, Bohan Yang
An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. Sci. China Inf. Sci. 65(4) (2022) - [j143]Huiyu Mo
A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. IEEE J. Solid State Circuits 57(5): 1542-1557 (2022) - [j142]Jung-Hwan Choi, Po-Chiun Huang
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 57(10): 2895-2897 (2022) - [j141]Yang Wang
Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning. IEEE J. Solid State Circuits 57(10): 3164-3178 (2022) - [j140]Zongsheng Hou
Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2024-2037 (2022) - [j139]Baofen Yuan
Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2929-2942 (2022) - [j138]Ang Li
BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4747-4757 (2022) - [j137]Yong Wu, Honglan Jiang
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2655-2668 (2022) - [j136]Zhiheng Yue
BR-CIM: An Efficient Binary Representation Computation-In-Memory Design. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3940-3953 (2022) - [j135]Yang Wang
SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 4014-4027 (2022) - [j134]Yang Wang
PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 4042-4055 (2022) - [j133]Jianxun Yang
GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 4069-4082 (2022) - [j132]Xiangren Chen, Bohan Yang
CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 94-126 (2022) - [j131]Cankun Zhao
A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 270-295 (2022) - [c132]Xiangren Chen, Bohan Yang
Efficient access scheme for multi-bank based NTT architecture through conflict graph. DAC 2022: 91-96 - [c131]Jinyi Deng
Mixed-granularity parallel coarse-grained reconfigurable architecture. DAC 2022: 343-348 - [c130]Zhiheng Yue, Yabing Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation. DAC 2022: 457-462 - [c129]Shixuan Zheng, Xianjue Zhang, Leibo Liu, Shaojun Wei, Shouyi Yin:
Atomic Dataflow based Graph-Level Workload Orchestration for Scalable DNN Accelerators. HPCA 2022: 475-489 - [c128]Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Jianfeng Zhu, Honglan Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu:
Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. HPCA 2022: 986-1000 - [c127]Mingyuan Yang, Yemeng Zhang, Bohan Yang
A SHA-512 Hardware Implementation Based on Block RAM Storage Structure. IPDPS Workshops 2022: 132-135 - [c126]Xingchen Man
CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process. ISCA 2022: 259-273 - [c125]Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. ISSCC 2022: 1-3 - [c124]Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin:
A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing. ISSCC 2022: 1-3 - [c123]Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. ISSCC 2022: 466-468 - [c122]Yihong Zhu, Wenping Zhu, Min Zhu, Chongyang Li, Chenchen Deng, Chen Chen
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems. ISSCC 2022: 514-516 - [i6]Hongjiang Chen, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
FAQS: Communication-efficient Federate DNN Architecture and Quantization Co-Search for personalized Hardware-aware Preferences. CoRR abs/2210.08450 (2022) - [i5]Hongjiang Chen, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
HQNAS: Auto CNN deployment framework for joint quantization and architecture search. CoRR abs/2210.08485 (2022) - 2021
- [j130]Hai Huang, Leibo Liu, Min Zhu, Shouyi Yin, Shaojun Wei:
Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers. Sci. China Inf. Sci. 64(8) (2021) - [j129]Fengbin Tu
Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. IEEE J. Solid State Circuits 56(2): 658-673 (2021) - [j128]Jianfeng Zhu, Ao Luo, Guanhua Li, Bowei Zhang, Yong Wang, Gang Shan, Yi Li, Jianfeng Pan, Chenchen Deng, Shouyi Yin, Shaojun Wei, Leibo Liu:
Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters. IEEE J. Solid State Circuits 56(8): 2585-2601 (2021) - [j127]Fengbin Tu
Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". IEEE J. Solid State Circuits 56(9): 2895 (2021) - [j126]Jianxun Yang
TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. IEEE J. Solid State Circuits 56(10): 3021-3038 (2021) - [j125]Neng Zhang
Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1896-1908 (2021) - [j124]Yibo Wu
A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2170-2183 (2021) - [j123]Kai Zhou
Flexible Rectification of a Speckle Projection System for Depth Sensing. IEEE Trans. Instrum. Meas. 70: 1-13 (2021) - [j122]Huiyu Mo
A 460 GOPS/W Improved Mnemonic Descent Method-Based Hardwired Accelerator for Face Alignment. IEEE Trans. Multim. 23: 1122-1135 (2021) - [j121]Longlong Chen
An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Parallel Distributed Syst. 32(12): 3066-3080 (2021) - [c121]Yang Wang, Dazheng Deng, Leibo Liu, Shaojun Wei, Shouyi Yin:
LPE: Logarithm Posit Processing Element for Energy-Efficient Edge-Device Training. AICAS 2021: 1-4 - [c120]Yang Wang, Yubin Qin, Leibo Liu, Shaojun Wei, Shouyi Yin:
HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning. AICAS 2021: 1-4 - [c119]Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei:
Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. ASP-DAC 2021: 204-209 - [c118]Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei:
A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. ASP-DAC 2021: 229-234 - [c117]Huiyu Shi, Xi Chen, Tianlong Kong, Shouyi Yin, Peng Ouyang:
GLMSnet: Single Channel Speech Separation Framework in Noisy and Reverberant Environments. ASRU 2021: 663-670 - [c116]Zhendong Wang, Rujia Wang, Zihang Jiang
Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption. ATS 2021: 115-120 - [c115]Xinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin:
ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training. DAC 2021: 751-756 - [c114]Haichang Yang, Zhaoshi Li, Jiawei Wang, Shouyi Yin, Shaojun Wei, Leibo Liu:
HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms. DATE 2021: 834-837 - [c113]Jianxun Yang
FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks. HPCA 2021: 894-907 - [c112]Dajiang Liu, Ting Liu, Xingyu Mo, Jiaxing Shang, Shouyi Yin:
Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs. ICCAD 2021: 1-9 - [c111]Hao Sun, Yujuan Cheng, Yang Wang, Bin Wang, Shouyi Yin:
Learnable Quantization Loss Function Based on Expectation. ICAC 2021: 1-6 - [c110]Tianlong Kong, Shouyi Yin, Dawei Zhang, Wang Geng, Xin Wang, Dandan Song, Jinwen Huang, Huiyu Shi, Xiaorui Wang:
Dynamic Multi-Scale Convolution for Dialect Identification. Interspeech 2021: 3261-3265 - [c109]Weiyi Sun, Zhaoshi Li, Shouyi Yin, Shaojun Wei, Leibo Liu:
ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast. ISCA 2021: 237-250 - [c108]Huiyu Mo, Wenping Zhu, Wenjing Hu, Guangbin Wang, Qiang Li, Ang Li
9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. ISSCC 2021: 146-148 - [c107]Ruiqi Guo
15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. ISSCC 2021: 242-244 - [c106]Ruiqi Guo
A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation. VLSI Circuits 2021: 1-2 - [c105]Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Tianbao Chen, Xinhan Lin, Leibo Liu, Shaojun Wei, Shouyi Yin:
A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation. VLSI Circuits 2021: 1-2 - [i4]Tianlong Kong, Shouyi Yin, Dawei Zhang, Wang Geng, Xin Wang, Dandan Song, Jinwen Huang, Huiyu Shi, Xiaorui Wang:
Dynamic Multi-scale Convolution for Dialect Identification. CoRR abs/2108.07787 (2021) - 2020
- [j120]Leibo Liu
A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. ACM Comput. Surv. 52(6): 118:1-118:39 (2020) - [j119]Guiqiang Peng
A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection. IEEE J. Solid State Circuits 55(2): 505-519 (2020) - [j118]Neng Zhang
NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication. IEEE Trans. Computers 69(4): 520-533 (2020) - [j117]Shixuan Zheng
Efficient Scheduling of Irregular Network Structures on CNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3408-3419 (2020) - [j116]Zhendong Wang
Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3433-3444 (2020) - [j115]Chenchen Deng
A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 375-379 (2020) - [j114]Hang Wang, Xiang Li, Daqiang Han, Shiquan Yu, Shouyi Yin
A 4K × 2K@60fps Multifunctional Video Display Processor for High Perceptual Image Quality. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 451-463 (2020) - [j113]Neng Zhang, Bohan Yang, Chen Chen, Shouyi Yin, Shaojun Wei, Leibo Liu:
Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(2): 49-72 (2020) - [j112]Huiyu Mo
A Multi-Task Hardwired Accelerator for Face Detection and Alignment. IEEE Trans. Circuits Syst. Video Technol. 30(11): 4284-4298 (2020) - [j111]Liang Wang
Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings. IEEE Trans. Parallel Distributed Syst. 31(3): 611-622 (2020) - [j110]Leibo Liu
Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation. IEEE Trans. Parallel Distributed Syst. 31(12): 2981-2994 (2020) - [j109]Leibo Liu
Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems. IEEE Trans. Signal Process. 68: 573-588 (2020) - [j108]Pan Wang
Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation. IEEE Trans. Wirel. Commun. 19(2): 1025-1037 (2020) - [c104]Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin:
A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. A-SSCC 2020: 1-4 - [c103]Mingyang Kou
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. DAC 2020: 1-6 - [c102]Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. DAC 2020: 1-6 - [c101]Ning Li, Leibo Liu, Shaojun Wei, Shouyi Yin:
A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs. FCCM 2020: 243 - [c100]Peishuo Li, Zihang Jiang
PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement. ICASSP 2020: 6234-6238 - [c99]Yanan Lu, Leibo Liu, Jian Liu, Shouyi Yin, Shaojun Wei:
A Reconfigurable Branch Predictor for Spatial Computing Architectures. ICDSP 2020: 295-299 - [c98]Xi Chen, Songyang Zhang, Dandan Song, Peng Ouyang, Shouyi Yin:
Transformer with Bidirectional Decoder for Speech Recognition. INTERSPEECH 2020: 1773-1777 - [c97]Ruyun Li, Tianyu Liang
THUEE System for NIST SRE19 CTS Challenge. INTERSPEECH 2020: 2232-2236 - [c96]Yifan Yang, Zhaoshi Li, Yangdong Deng, Zhiwei Liu, Shouyi Yin, Shaojun Wei, Leibo Liu:
GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent. ISCA 2020: 419-432 - [c95]Dibei Chen, Zhaoshi Li, Tianzhu Xiong, Zhiwei Liu, Jun Yang, Shouyi Yin, Shaojun Wei, Leibo Liu:
CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. MICRO 2020: 342-355 - [c94]Huiyu Mo, Leibo Liu, Wenjing Hu, Wenping Zhu, Qiang Li, Ang Li
TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks. MICRO 2020: 751-765 - [i3]Xi Chen, Songyang Zhang, Dandan Song, Peng Ouyang, Shouyi Yin:
Transformer with Bidirectional Decoder for Speech Recognition. CoRR abs/2008.04481 (2020)
2010 – 2019
- 2019
- [j107]Shouyi Yin
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width. IEEE J. Solid State Circuits 54(4): 1120-1136 (2019) - [j106]Yinglin Zhao, Peng Ouyang
An STT-MRAM Based in Memory Architecture for Low Power Integral Computing. IEEE Trans. Computers 68(4): 617-623 (2019) - [j105]Hai Huang, Leibo Liu
Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 208-219 (2019) - [j104]Shouyi Yin
A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 678-691 (2019) - [j103]Leibo Liu
A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1265-1277 (2019) - [j102]Liang Wang
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1771-1784 (2019) - [j101]Dajiang Liu
Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2271-2283 (2019) - [j100]Man Shi, Peng Ouyang
A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression. IEEE Trans. Circuits Syst. II Express Briefs 66-II(11): 1870-1874 (2019) - [j99]Shixuan Zheng
An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4648-4661 (2019) - [j98]Fengbin Tu
Reconfigurable Architecture for Neural Approximation in Multimedia Computing. IEEE Trans. Circuits Syst. Video Technol. 29(3): 892-906 (2019) - [j97]Leibo Liu
A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching. IEEE Trans. Circuits Syst. Video Technol. 29(8): 2467-2481 (2019) - [j96]Huiyu Mo
Face Alignment With Expression- and Pose-Based Adaptive Initialization. IEEE Trans. Multim. 21(4): 943-956 (2019) - [j95]Shouyi Yin
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. 30(1): 146-160 (2019) - [c93]Xi Chen, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei:
Small-Footprint Keyword Spotting with Graph Convolutional Network. ASRU 2019: 539-546 - [c92]Hui Yan, Zhaoshi Li, Leibo Liu
Constructing Concurrent Data Structures on FPGA with Channels. FPGA 2019: 172-177 - [c91]Yu Pan, Peng Ouyang, Yinglin Zhao, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao:
A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network. ACM Great Lakes Symposium on VLSI 2019: 271-274 - [c90]Leibo Liu
Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor. Hot Chips Symposium 2019: 1-25 - [c89]Kai Lu, Zhaoshi Li, Leibo Liu
ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms. ICCAD 2019: 1-8 - [c88]Hang Yuan, Wei Guo, Chip-Hong Chang
A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. ISCAS 2019: 1-5 - [c87]Jun Yang, Yuyao Kong, Zhen Wang, Yan Liu, Bo Wang, Shouyi Yin, Longxin Shi:
Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation. ISSCC 2019: 394-396 - [c86]Feng Xiong, Fengbin Tu, Shouyi Yin, Shaojun Wei:
Towards Efficient Compact Network Training on Edge-Devices. ISVLSI 2019: 61-67 - [c85]Zhaoshi Li, Leibo Liu
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. MICRO 2019: 911-923 - [c84]Jianxun Yang
An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks. NANOARCH 2019: 1-6 - [c83]Weiwei Wu, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei:
MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions. NEWCAS 2019: 1-4 - [c82]Ruiqi Guo
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. VLSI Circuits 2019: 120- - [i2]Xi Chen, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei:
Small-footprint Keyword Spotting with Graph Convolutional Network. CoRR abs/1912.05124 (2019) - [i1]Yi Liu, Tianyu Liang, Can Xu, Xianwei Zhang, Xianhong Chen, Wei-Qiang Zhang, Liang He, Dandan Song, Ruyun Li, Yangcheng Wu, Peng Ouyang, Shouyi Yin:
THUEE system description for NIST 2019 SRE CTS Challenge. CoRR abs/1912.11585 (2019) - 2018
- [j94]Shouyi Yin, Tianyi Lu
Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. IEEE Access 6: 7526-7540 (2018) - [j93]Zhaoshi Li
Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution. IEEE Comput. Archit. Lett. 17(2): 147-150 (2018) - [j92]Shuang Liang
FP-BNN: Binarized neural network on FPGA. Neurocomputing 275: 1072-1086 (2018) - [j91]Ruofei Hu, Binren Tian, Shouyi Yin, Shaojun Wei:
Optimization of Softmax Layer in Deep Neural Network Using Integral Stochastic Computation. J. Low Power Electron. 14(4): 475-480 (2018) - [j90]Shouyi Yin
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. IEEE J. Solid State Circuits 53(4): 968-982 (2018) - [j89]Shouyi Yin
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 431-444 (2018) - [j88]Leibo Liu
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 782-795 (2018) - [j87]Leibo Liu
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1171-1184 (2018) - [j86]Jiale Yan, Shouyi Yin
GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2519-2529 (2018) - [j85]Leibo Liu
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3081-3094 (2018) - [j84]Leibo Liu
HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 381-385 (2018) - [j83]Guiqiang Peng
A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1717-1730 (2018) - [j82]Peng Ouyang
A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3362-3375 (2018) - [j81]Jiangyuan Gu
Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration. IEEE Trans. Parallel Distributed Syst. 29(9): 2105-2120 (2018) - [j80]Yanan Lu
Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. 29(10): 2360-2372 (2018) - [j79]Guiqiang Peng
Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems. IEEE Trans. Signal Process. 66(7): 1860-1875 (2018) - [j78]Shouyi Yin
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2345-2357 (2018) - [c81]Hang Wang, Hongbin Sun, Xuchong Zhang, Qiubo Chen, Pengju Ren, Xiaogang Wu, Shouyi Yin, Zhiqiang Jiang, Xiang Li, Daqiang Han, Shiquan Yu, Shaojun Wei, Nanning Zheng:
A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality. APCCAS 2018: 427-430 - [c80]Guiqiang Peng, Leibo Liu
A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems. A-SSCC 2018: 191-194 - [c79]Hang Yuan, Leibo Liu
A Full Multicast Reconfigurable Non-blocking Permutation Network. CyberC 2018 - [c78]Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu
LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. DAC 2018: 16:1-16:6 - [c77]Shixuan Zheng, Yonggang Liu, Shouyi Yin, Leibo Liu
An efficient kernel transformation architecture for binary- and ternary-weight neural network inference. DAC 2018: 137:1-137:6 - [c76]Ruofei Hu, Binren Tian, Shouyi Yin, Shaojun Wei:
Efficient Hardware Architecture of Softmax Layer in Deep Neural Network. DSP 2018: 1-5 - [c75]Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu
RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. ISCA 2018: 340-352 - [c74]Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu
Bit-width Adaptive Accelerator Design for Convolution Neural Network. ISCAS 2018: 1-5 - [c73]Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu
An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. ISCAS 2018: 1-5 - [c72]Shouyi Yin, Peng Ouyang, Jianxun Yang
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS. VLSI Circuits 2018: 37-38 - [c71]Shouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu
A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS. VLSI Circuits 2018: 139-140 - 2017
- [j77]Weizhi Xu
Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion. IEEE Access 5: 26604-26613 (2017) - [j76]Leibo Liu
Implementation of in-loop filter for HEVC decoder on reconfigurable processor. IET Image Process. 11(9): 685-692 (2017) - [j75]Shouyi Yin, Peng Ouyang, Xu Dai
An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation. IEEE Syst. J. 11(1): 260-271 (2017) - [j74]Chenchen Deng
PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC. IEEE Trans. Circuits Syst. II Express Briefs 64-II(5): 540-544 (2017) - [j73]Bo Wang, Leibo Liu
Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. IEEE Trans. Inf. Forensics Secur. 12(2): 309-322 (2017) - [j72]Chen Yang, Leibo Liu
CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. 28(1): 29-43 (2017) - [j71]Chen Wu, Chenchen Deng, Leibo Liu
A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. IEEE Trans. Parallel Distributed Syst. 28(3): 662-676 (2017) - [j70]Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. IEEE Trans. Parallel Distributed Syst. 28(9): 2471-2485 (2017) - [j69]Guiqiang Peng, Leibo Liu
Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture. IEEE Trans. Signal Process. 65(14): 3775-3788 (2017) - [j68]Fengbin Tu
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2220-2233 (2017) - [c70]Jiangyuan Gu, Shouyi Yin, Leibo Liu
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. ASP-DAC 2017: 312-317 - [c69]Jiangyuan Gu, Shouyi Yin, Shaojun Wei:
Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. DAC 2017: 40:1-40:6 - [c68]Peng Ouyang, Shouyi Yin, Shaojun Wei:
A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications. DAC 2017: 63:1-63:6 - [c67]Shouyi Yin, Zhicong Xie, Shaojun Wei:
Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. DAC 2017: 84:1-84:6 - [c66]Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu
Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. FCCM 2017: 31 - [c65]Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). FPGA 2017: 290 - [c64]Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei:
Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). FPGA 2017: 295 - [c63]Peng Ouyang, Shouyi Yin, Chunxiao Xing
A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation. ACM Great Lakes Symposium on VLSI 2017: 287-292 - [c62]Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei:
Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. ISCA 2017: 575-586 - [c61]Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu
Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS 2017: 1-4 - [c60]Shouyi Yin, Dajiang Liu, Lifeng Sun, Leibo Liu
DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. ISCAS 2017: 1-4 - [c59]Shibin Tang, Shouyi Yin, Shixuan Zheng, Peng Ouyang, Fengbin Tu, Leiyue Yao, JinZhou Wu, Wenming Cheng, Leibo Liu
AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. NVMSA 2017: 1-6 - [c58]Shouyi Yin, Jinjin Duan, Peng Ouyang, Leibo Liu
Multi-CNN and decision tree based driving behavior evaluation. SAC 2017: 1424-1429 - 2016
- [j67]Shuang Liang, Shouyi Yin, Leibo Liu
A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. IEEE Comput. Archit. Lett. 15(2): 69-72 (2016) - [j66]Peng Ouyang, Shouyi Yin, Chenchen Deng, Leibo Liu
A fast face detection architecture for auto-focus in smart-phones and digital cameras. Sci. China Inf. Sci. 59(12): 122402:1-122402:13 (2016) - [j65]Leibo Liu
An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. IEICE Trans. Inf. Syst. 99-D(5): 1285-1295 (2016) - [j64]Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu
Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1475-1488 (2016) - [j63]Shouyi Yin, Peng Ouyang, Leibo Liu
A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 668-672 (2016) - [j62]Wenping Zhu, Leibo Liu
A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator. IEEE Trans. Circuits Syst. Video Technol. 26(8): 1532-1543 (2016) - [j61]Bo Wang, Leibo Liu
Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture. IEEE Trans. Inf. Forensics Secur. 11(6): 1151-1164 (2016) - [j60]Leibo Liu
TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. IEEE Trans. Parallel Distributed Syst. 27(7): 2143-2154 (2016) - [j59]Shouyi Yin, Xinhan Lin, Leibo Liu
Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Parallel Distributed Syst. 27(11): 3199-3213 (2016) - [j58]Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu
Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 507-520 (2016) - [j57]Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1305-1318 (2016) - [j56]Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1895-1908 (2016) - [j55]Shouyi Yin, Pengcheng Zhou, Leibo Liu
Trigger-Centric Loop Mapping on CGRAs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1998-2002 (2016) - [j54]Shouyi Yin, Weizhi Xu, Jiakun Li, Leibo Liu
CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2548-2561 (2016) - [c57]Xinhan Lin, Shouyi Yin, Leibo Liu
Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. ASP-DAC 2016: 456-461 - [c56]Chen Yang, Leibo Liu
Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. DAC 2016: 64:1-64:6 - [c55]Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu
Multibank memory optimization for parallel data access in multiple data arrays. ICCAD 2016: 32 - [c54]Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu
Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD 2016: 127 - [c53]Peng Ouyang, Shouyi Yin, Chunxiao Xing
Energy management on DVS based coarse-grained reconfigurable platform. NANOARCH 2016: 49-54 - 2015
- [j53]Chen Wu, Chenchen Deng, Leibo Liu
Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints. Sci. China Inf. Sci. 58(8): 1-14 (2015) - [j52]Yu Peng, Shouyi Yin, Leibo Liu
Battery-Aware Loop Nests Mapping for CGRAs. IEICE Trans. Inf. Syst. 98-D(2): 230-242 (2015) - [j51]Bing Xu
Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD. IEICE Trans. Inf. Syst. 98-D(2): 243-251 (2015) - [j50]Rui Shi, Shouyi Yin, Leibo Liu
The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture. IEICE Trans. Inf. Syst. 98-D(2): 276-287 (2015) - [j49]Dajiang Liu, Shouyi Yin, Leibo Liu
Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1419-1430 (2015) - [j48]Chen Yang, Leibo Liu
Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. J. Circuits Syst. Comput. 24(3): 1550043:1-1550043:21 (2015) - [j47]Shouyi Yin, Peng Ouyang, Leibo Liu
Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature. Sensors 15(1): 2161-2180 (2015) - [j46]Shouyi Yin, Hao Dong, Guangli Jiang, Leibo Liu
A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps. Sensors 15(7): 15246-15264 (2015) - [j45]Weizhi Xu, Shouyi Yin, Leibo Liu
High-Performance Motion Estimation for Image Sensors with Video Compression. Sensors 15(8): 20752-20778 (2015) - [j44]Guangli Jiang, Leibo Liu
A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction. Sensors 15(9): 22509-22529 (2015) - [j43]Chen Wu, Chenchen Deng, Leibo Liu
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(8): 1264-1277 (2015) - [j42]Peng Ouyang, Shouyi Yin, Yuchi Zhang, Leibo Liu
A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 75-79 (2015) - [j41]Zhen Zhang, Shouyi Yin, Leibo Liu
A real-time time-consistent 2D-to-3D video conversion system using color histogram. IEEE Trans. Consumer Electron. 61(4): 524-530 (2015) - [j40]Leibo Liu
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. IEEE Trans. Multim. 17(10): 1706-1720 (2015) - [j39]Leibo Liu
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". IEEE Trans. Multim. 17(12): 2354-2355 (2015) - [j38]Yu Ren, Leibo Liu
Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm. ACM Trans. Reconfigurable Technol. Syst. 8(3): 19:1-19:24 (2015) - [j37]Jianfeng Zhu, Leibo Liu
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1700-1709 (2015) - [j36]Leibo Liu
A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2566-2580 (2015) - [j35]Dajiang Liu, Shouyi Yin, Yu Peng, Leibo Liu
Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2581-2594 (2015) - [j34]Peng Ouyang, Shouyi Yin, Leibo Liu
Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3085-3098 (2015) - [c52]Leibo Liu
A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures. ASP-DAC 2015: 48-53 - [c51]Yu Peng, Shouyi Yin, Leibo Liu
Battery-aware mapping optimization of loop nests for CGRAs. ASP-DAC 2015: 767-772 - [c50]Shouyi Yin, Peng Ouyang, Leibo Liu
A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space. CICC 2015: 1-4 - [c49]Junbin Wang, Leibo Liu
Acceleration of control flows on reconfigurable architecture with a composite method. DAC 2015: 45:1-45:6 - [c48]Guangli Jiang, Leibo Liu
A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction. DAC 2015: 87:1-87:6 - [c47]Chenyue Meng, Shouyi Yin, Peng Ouyang, Leibo Liu
Efficient memory partitioning for parallel data access in multidimensional arrays. DAC 2015: 160:1-160:6 - [c46]Shouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei, Yike Guo:
Joint affine transformation and loop pipelining for mapping nested loop on CGRAs. DATE 2015: 115-120 - [c45]Shouyi Yin, Jiakun Li, Leibo Liu, Shaojun Wei, Yike Guo:
Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache. DATE 2015: 187-192 - [c44]Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
RNA: a reconfigurable architecture for hardware neural acceleration. DATE 2015: 695-700 - [c43]Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei:
Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). FPGA 2015: 263 - [c42]Leibo Liu, Yingjie Victor Chen, Dong Wang, Min Zhu, Shouyi Yin, Shaojun Wei:
A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). FPGA 2015: 267 - [c41]Junbin Wang, Leibo Liu
A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only). FPGA 2015: 270 - [c40]Shouyi Yin, Pengcheng Zhou, Leibo Liu
Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. ICCAD 2015: 597-604 - [c39]Hao Dong, Shouyi Yin, Guangli Jiang, Leibo Liu
An automatic depth map generation method by image classification. ICCE 2015: 168-169 - [c38]Zhen Zhang, Shouyi Yin, Leibo Liu
Real-time time-consistent 2D-to-3D video conversion based on color histogram. ICCE 2015: 188-189 - [c37]Tao Tan, Shouyi Yin, Peng Ouyang, Leibo Liu
Efficient lane detection system based on monocular camera. ICCE 2015: 202-203 - [c36]Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu
Neural approximating architecture targeting multiple application domains. ISCAS 2015: 2509-2512 - [c35]Xu Dai
A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor. WACV 2015: 657-662 - 2014
- [j33]Shanshan Cai, Leibo Liu
Optimization of speeded-up robust feature algorithm for hardware implementation. Sci. China Inf. Sci. 57(4): 1-15 (2014) - [j32]Leibo Liu
Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor. Sci. China Inf. Sci. 57(8): 1-14 (2014) - [j31]Leibo Liu
Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system. Sci. China Inf. Sci. 57(8): 1-14 (2014) - [j30]Leibo Liu
Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture. Sci. China Inf. Sci. 57(10): 1-18 (2014) - [j29]Shouyi Yin, Shengjia Shao, Leibo Liu
MapReduce inspired loop mapping for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. 57(12): 1-14 (2014) - [j28]Ruoyu Xu, Wai Chiu Ng, George Jie Yuan, Shouyi Yin, Shaojun Wei:
A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision. IEEE J. Solid State Circuits 49(10): 2342-2351 (2014) - [j27]Shouyi Yin, Xu Dai
A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps. Sensors 14(10): 19561-19581 (2014) - [j26]Leibo Liu
An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices. IEEE Trans. Consumer Electron. 60(1): 137-145 (2014) - [j25]Yansheng Wang, Leibo Liu
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 983-994 (2014) - [j24]Leibo Liu
SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2635-2648 (2014) - [c34]Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms. DATE 2014: 1-6 - [c33]Dajiang Liu, Shouyi Yin, Leibo Liu
Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures. FCCM 2014: 32 - [c32]Chenchen Deng, Leibo Liu
Teach Reconfigurable Computing using mixed-grained fabrics based hardware infrastructure. FIE 2014: 1-9 - [c31]Chen Yang, Leibo Liu
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. FPL 2014: 1-4 - [c30]Peng Ouyang, Shouyi Yin, Leibo Liu
A FAST Extreme Illumination Robust Feature in Affine Space. ICPR 2014: 2365-2370 - [c29]Shengjia Shao, Shouyi Yin, Leibo Liu
Map-reduce inspired loop parallelization on CGRA. ISCAS 2014: 1231-1234 - [c28]Yuchi Zhang, Shouyi Yin, Peng Ouyang, Leibo Liu
A parallel hardware architecture for fast integral image computing. ISCAS 2014: 2189-2192 - [c27]Wenping Zhu, Leibo Liu
A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing. ISCAS 2014: 2527-2530 - [c26]Bing Xu
Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD. MWSCAS 2014: 242-245 - [c25]Shouyi Yin, Peng Ouyang, Leibo Liu
A fast and robust traffic sign recognition method using ring of RIBP histograms based feature. ROBIO 2014: 2570-2575 - 2013
- [j23]Leibo Liu
ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor. Sci. China Inf. Sci. 56(6): 1-16 (2013) - [j22]Weilong Zhang, Leibo Liu
An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video. Sci. China Inf. Sci. 56(7): 1-14 (2013) - [j21]Yansheng Wang, Leibo Liu
Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. 56(11): 1-20 (2013) - [j20]Jienan Zhang, Shouyi Yin, Peng Ouyang, Leibo Liu
Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1357-1365 (2013) - [j19]Peng Ouyang, Shouyi Yin, Hui Gao, Leibo Liu
Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1393-1402 (2013) - [j18]Shouyi Yin, Dajiang Liu, Leibo Liu
Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs. IEICE Trans. Inf. Syst. 96-D(8): 1582-1591 (2013) - [j17]Yansheng Wang, Leibo Liu
The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(11): 2218-2229 (2013) - [j16]Shouyi Yin, Rui Shi, Leibo Liu
Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture. IEICE Trans. Inf. Syst. 96-D(12): 2524-2535 (2013) - [j15]Zhen Zhang, Shouyi Yin, Leibo Liu
An Inductive-Coupling Interconnected Application-Specific 3D NoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2633-2644 (2013) - [j14]Shouyi Yin, Jianwei Cui, Leibo Liu
Calibration Techniques for Low-Power Wireless Multiband Transceiver. Int. J. Distributed Sens. Networks 9 (2013) - [j13]Yu Ren, Leibo Liu
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration. J. Syst. Archit. 59(7): 482-491 (2013) - [j12]Wei Xia, Shouyi Yin, Peng Ouyang:
A High Precision Feature Based on LBP and Gabor Theory for Face Recognition. Sensors 13(4): 4499-4513 (2013) - [j11]Jianfeng Zhu, Leibo Liu
Low-Power Reconfigurable Processor Utilizing Variable Dual VDD. IEEE Trans. Circuits Syst. II Express Briefs 60-II(4): 217-221 (2013) - [c24]Leibo Liu
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. CICC 2013: 1-4 - [c23]Leibo Liu
SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process. CICC 2013: 1-4 - [c22]Dajiang Liu, Shouyi Yin, Leibo Liu
Polyhedral model based mapping optimization of loop nests for CGRAs. DAC 2013: 19:1-19:8 - [c21]Guoyong Li, Leibo Liu
Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding. EMC/HumanCom 2013: 545-555 - [c20]Zhen Zhang, Shouyi Yin, Leibo Liu
An inductive-coupling interconnected application-specific 3D NoC design. ISCAS 2013: 550-553 - [c19]Leibo Liu
Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor. ISCAS 2013: 897-900 - [c18]Yu Ren, Leibo Liu
A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration. ISCAS 2013: 1793-1796 - [c17]Dajiang Liu, Shouyi Yin, Leibo Liu
Affine transformations for communication and reconfiguration optimization of loops on CGRAs. ISCAS 2013: 2541-2544 - [c16]Qinghua Wu, Leibo Liu
SPC: An Approach to Guarantee Performance in Cost Oriented Mapping Algorithm for NoC Architectures. NAS 2013: 187-190 - [c15]Yulin Li, Shouyi Yin, Leibo Liu
Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network. NAS 2013: 297-301 - 2012
- [j10]Shouyi Yin, Chongyong Yin, Leibo Liu
Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture. IEICE Trans. Inf. Syst. 95-D(2): 335-344 (2012) - [j9]Shouyi Yin, Yang Hu, Zhen Zhang, Leibo Liu
Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC. IEICE Trans. Electron. 95-C(4): 495-505 (2012) - [j8]Peng Ouyang, Shouyi Yin, Leibo Liu
Multi-Battery Scheduling for Battery-Powered DVS Systems. IEICE Trans. Commun. 95-B(7): 2278-2285 (2012) - [j7]Dajiang Liu, Shouyi Yin, Chongyong Yin, Leibo Liu
Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture. IEICE Trans. Inf. Syst. 95-D(12): 2898-2907 (2012) - [c14]Shouyi Yin, Chongyong Yin, Leibo Liu
Reducing configuration contexts for coarse-grained reconfigurable architecture. ISCAS 2012: 121-124 - 2011
- [c13]Shouyi Yin, Jianwei Cui, Ao Luo, Leibo Liu
A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems. ASICON 2011: 224-227 - [c12]Shuang Liang, Shouyi Yin, Chongyong Yin, Leibo Liu
Performance evaluation modeling for reconfigurable processor. ASICON 2011: 570-573 - 2010
- [j6]Shouyi Yin, Zhongfu Sun, Leibo Liu
CropNET: A Wireless Multimedia Sensor Network for Agricultural Monitoring. IEICE Trans. Commun. 93-B(8): 2073-2076 (2010) - [j5]Min Zhu, Leibo Liu
A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System. IEICE Trans. Inf. Syst. 93-D(12): 3202-3210 (2010) - [j4]Tongsheng Geng, Leibo Liu
Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System. IEICE Trans. Inf. Syst. 93-D(12): 3223-3231 (2010) - [c11]Peng Ouyang, Shouyi Yin, Leibo Liu
Battery aware tasks allocating algorithm for multi-battery operated system. APCCAS 2010: 875-878 - [c10]Yang Hu, Shouyi Yin, Leibo Liu
Mixed-level modeling for network on chip infrastructure in SoC design. APCCAS 2010: 911-914 - [c9]Shouyi Yin, Tao Liu, Huafeng Wei, Guang Ji:
Syndrome differentiation of fatty liver based on the whole network analysis theory. BIBM Workshops 2010: 598-602 - [c8]Renyan Zhou, Leibo Liu
A VLSI design of sensor node for wireless image sensor network. ISCAS 2010: 149-152 - [c7]Tongsheng Geng, Leibo Liu
Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC. ISCAS 2010: 1153-1156 - [c6]Min Zhu, Leibo Liu
A reconfigurable multi-processor SoC for media applications. ISCAS 2010: 2011-2014
2000 – 2009
- 2009
- [j3]Shouyi Yin, Leibo Liu
Buffer planning for application-specific networks-on-chip design. Sci. China Ser. F Inf. Sci. 52(4): 547-558 (2009) - [j2]Chongyong Yin, Shouyi Yin, Leibo Liu
Compiler Framework for Reconfigurable Computing Architecture. IEICE Trans. Electron. 92-C(10): 1284-1290 (2009) - 2006
- [j1]Shouyi Yin, Yongqiang Xiong, Qian Zhang
Traffic-aware routing for real-time communications in wireless multi-hop networks. Wirel. Commun. Mob. Comput. 6: 825-843 (2006) - [c5]Shouyi Yin, Yongqiang Xiong, Qian Zhang
Prediction-based routing for real time communications in wireless multi-hop networks. QSHINE 2006: 28 - [c4]Shouyi Yin, Yongqiang Xiong, Xiaokang Lin, Qian Zhang:
Traffic-aware Routing for Real Time Communications in Wireless Multi-hop Networks. SUTC (1) 2006: 568-569 - 2005
- [c3]Shouyi Yin, Xiaokang Lin:
Multipath minimum energy routing in ad hoc network. ICC 2005: 3182-3186 - [c2]Shouyi Yin, Xiaokang Lin:
Multipath Energy Efficient Routing in Mobile Ad Hoc Network. ICN (2) 2005: 226-233 - [c1]Shouyi Yin, Xiaokang Lin:
Adaptive load balancing in mobile ad hoc networks. WCNC 2005: 1982-1987
Coauthor Index
[j158] [j157] [j156] [j155] [j154] [j153] [j152] [j151] [j150] [j148] [j147] [j146] [j145] [c145] [c144] [c143] [c142] [c140] [c139] [c138] [c137] [c136] [c135] [c134] [c133] [i9] [i8] [j144] [j143] [j141] [j140] [j139] [j138] [j137] [j136] [j135] [j134] [j133] [j132] [j131] [c132] [c131] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [c122] [i6] [i5] [j130] [j129] [j128] [j127] [j126] [j125] [j124] [j122] [j121] [c121] [c120] [c119] [c118] [c115] [c114] [c113] [c109] [c108] [c107] [c106] [c105] [j120] [j119] [j118] [j117] [j115] [j113] [j112] [j111] [j110] [j109] [j108] [c104] [c102] [c101] [c100] [c99] [c96] [c95] [c94] [j107] [j105] [j104] [j103] [j102] [j101] [j100] [j99] [j98] [j97] [j96] [j95] [c93] [c92] [c90] [c89] [c88] [c85] [c84] [c83] [c82] [i2] [j94] [j93] [j92] [j90] [j89] [j88] [j87] [j86] [j85] [j84] [j83] [j82] [j81] [j80] [j79] [j78] [c80] [c79] [c78] [c77] [c75] [c74] [c73] [c72] [c71] [j77] [j76] [j75] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [c70] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [j67] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [c57] [c56] [c55] [c54] [c53] [j53] [j52] [j51] [j50] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [j33] [j32] [j31] [j30] [j29] [j27] [j26] [j25] [j24] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [j11] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [j10] [j9] [j8] [j7] [c14] [c13] [c12] [j6] [j5] [j4] [c11] [c10] [c8] [c7] [c6] [j3] [j2]
[c155] [j123] [c117] [c100] [c98] [c97] [i3] [j107] [j106] [j104] [j100] [j99] [j98] [j95] [c93] [c91] [c82] [i2] [i1] [j90] [j89] [j82] [c74] [c72] [c71] [j75] [j68] [c68] [c66] [c63] [c59] [c58] [j66] [j63] [j57] [c53] [j47] [j42] [j34] [c50] [c47] [c44] [c37] [c36] [c35] [j27] [c34] [c30] [c28] [c25] [j20] [j19] [j12] [j8] [c11]
[j159] [j158] [j157] [j156] [c158] [c157] [c154] [c153] [c152] [c151] [c150] [c149] [c148] [c147] [c146] [i13] [j155] [j154] [j153] [j152] [j151] [j150] [j149] [j148] [j147] [j146] [j145] [c145] [c144] [c143] [c142] [c140] [c139] [c138] [c137] [c136] [c135] [c134] [c133] [i9] [i8] [i7] [j144] [j143] [j141] [j140] [j139] [j138] [j137] [j136] [j135] [j134] [j133] [j132] [j131] [c132] [c131] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [c122] [i6] [i5] [j130] [j129] [j128] [j127] [j126] [j125] [j124] [j122] [j121] [c121] [c120] [c119] [c118] [c115] [c114] [c113] [c109] [c108] [c107] [c106] [c105] [j120] [j119] [j118] [j117] [j115] [j114] [j113] [j112] [j111] [j110] [j109] [j108] [c104] [c103] [c102] [c101] [c100] [c99] [c96] [c95] [c94] [j107] [j106] [j105] [j104] [j103] [j102] [j101] [j100] [j99] [j98] [j97] [j96] [j95] [c93] [c92] [c91] [c90] [c89] [c88] [c86] [c85] [c84] [c83] [c82] [i2] [j94] [j93] [j92] [j91] [j90] [j89] [j88] [j87] [j86] [j85] [j84] [j83] [j82] [j81] [j80] [j79] [j78] [c81] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [j77] [j76] [j75] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [j67] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [c57] [c56] [c55] [c54] [c53] [j53] [j52] [j51] [j50] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [j33] [j32] [j31] [j30] [j29] [j28] [j27] [j25] [j24] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [j11] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [j10] [j9] [j8] [j7] [c14] [c13] [c12] [j6] [j5] [j4] [c11] [c10] [c8] [c7] [c6] [j3] [j2]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-23 20:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: