One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. - Shin, Insup; Kim, Jae-Joon; Lin, Yu-Shiang; Shin, Youngsoo (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. - Shin, Insup; Kim, Jae-Joon; Shin, Youngsoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. - Shin, Youngsoo; Shin, Insup; Baek, Donkyu; Kim, Duckhwan; Paik, Seungwhun (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. - Shin, Insup; Kim, Jae-Joon; Shin, Youngsoo (2014)

Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. - Baek, Donkyu; Shin, Insup; Shin, Youngsoo (J. Circuits Syst. Comput., 2013)

A pipeline architecture with 1-cycle timing error correction for low voltage operations. - Shin, Insup; Kim, Jae-Joon; Lin, Yu-Shiang; Shin, Youngsoo (2013)

Synthesis of Active-Mode Power-Gating Circuits. - Seomun, Jun; Shin, Insup; Shin, Youngsoo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. - Shin, Insup; Paik, Seungwhun; Shin, Dongwan; Shin, Youngsoo (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Introducing irregularity to routing architecture of structured ASIC for better routability. - Shin, Insup; Baek, Donkyu; Shin, Youngsoo (2012)

Gate delay modeling for static timing analysis of body-biased circuits. - Baek, Donkyu; Shin, Insup; Shin, Youngsoo (2012)

Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. - Baek, Donkyu; Shin, Insup; Paik, Seungwhun; Shin, Youngsoo (2011)

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. - Paik, Seungwhun; Shin, Insup; Kim, Taewhan; Shin, Youngsoo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Synthesis and implementation of active mode power gating circuits. - Seomun, Jun; Shin, Insup; Shin, Youngsoo (2010)

Register allocation for high-level synthesis using dual supply voltages. - Shin, Insup; Paik, Seungwhun; Shin, Youngsoo (2009)

HLS-l: High-level synthesis of high performance latch-based circuits. - Paik, Seungwhun; Shin, Insup; Shin, Youngsoo (2009)